SN74LV123A

Name: SN74LV123A
Brand: TI
SKU: SN74LV123A
Price: 0.182 USD

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document-pdfAcrobat SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs datasheet (Rev. Q) (Inglés) PDF | HTML

SN74LV123A

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Detalles del producto

Number of channels

2

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Technology family

LV-A

Input type

Schmitt-Trigger

Output type

Push-Pull

Supply current (µA)

20

IOL (max) (mA)

12

IOH (max) (mA)

-12

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

2

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Technology family

LV-A

Input type

Schmitt-Trigger

Output type

Push-Pull

Supply current (µA)

20

IOL (max) (mA)

12

IOH (max) (mA)

-12

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable

Operating temperature range (°C)

-40 to 125

Rating

Catalog

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

SSOP (DB)

16

48.36 mm² 6.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

TVSOP (DGV)

16

23.04 mm² 3.6 x 6.4

VQFN (RGY)

16

14 mm² 4 x 3.5

2-V to 5.5-V V_CC Operation
Maximum t_pd of 11 ns at 5 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2.3 V at V_CC = 3.3 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR Inputs
for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
I_off Supports Partial-Power-Down Mode Operation
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class 11
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

2-V to 5.5-V V_CC Operation
Maximum t_pd of 11 ns at 5 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2.3 V at V_CC = 3.3 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR Inputs
for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
I_off Supports Partial-Power-Down Mode Operation
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class 11
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V_CC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low.

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V_CC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low.

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs datasheet (Rev. Q)	PDF \| HTML	31 ago 2015
	Product overview	Configurable Timed Reset Using Discrete Logic (Rev. A)	PDF \| HTML	02 may 2023
	Application note	Detect and Reset an Unresponsive Controller	PDF \| HTML	21 mar 2023
	Application note	Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A)	PDF \| HTML	13 mar 2020
	Selection guide	Logic Guide (Rev. AB)		12 jun 2017

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que esté en un empaquetado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML

No disponible en TI.com

Placa de evaluación

14-24-NL-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados sin conductores de 14 a 24 pine

14-24-NL-LOGIC-EVM es un módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo lógico o de traducción que tenga un encapsulado BQA, BQB, RGY, RSV, RJW o RHL de 14 a 24 pines.

Guía del usuario: PDF | HTML

No disponible en TI.com

Modelo de simulación

HSPICE Model for SN74LV123A

SCLJ019.ZIP (111 KB) - HSpice Model

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Modelo de simulación

SN74LV123A IBIS Model (Rev. A)

SCEM125A.ZIP (21 KB) - IBIS Model

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Modelo de simulación

SN74LV123A PSpice Model (Rev. C)

SCEM569C.ZIP (384 KB) - PSpice Model

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
SOIC (D)	16	Ultra Librarian
SOP (NS)	16	Ultra Librarian
SSOP (DB)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian
TVSOP (DGV)	16	Ultra Librarian
VQFN (RGY)	16	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

SN74LV123A

Multivibradores monoestables reiniciables dobles

SN74LV123A

Detalles del producto

Documentación técnica

Diseño y desarrollo

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

14-24-NL-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados sin conductores de 14 a 24 pine

HSPICE Model for SN74LV123A

SN74LV123A IBIS Model (Rev. A)

SN74LV123A PSpice Model (Rev. C)

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos