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SN74LVTH125

ACTIVO

Búferes de 4 canales, 2.7 V a 3.6 V con retención de bus, entradas CMOS compatibles con TTL y salida

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SN74LVTH125

ACTIVO
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Detalles del producto

Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 4 IOL (max) (mA) 64 Supply current (max) (µA) 7000 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 4 IOL (max) (mA) 64 Supply current (max) (µA) 7000 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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Documentación técnica

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Tipo Título Fecha
* Data sheet SN54LVTH125, SN74LVTH125 datasheet (Rev. I) 13 oct 2003
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 17 sep 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Simultaneous-Switching Performance of TI Logic Devices (Rev. B) 23 feb 2005
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 ene 2001
Application note LVT-to-LVTH Conversion 08 dic 1998
Application note LVT Family Characteristics (Rev. A) 01 mar 1998
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que esté en un empaquetado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML
No disponible en TI.com
Placa de evaluación

14-24-NL-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados sin conductores de 14 a 24 pine

14-24-NL-LOGIC-EVM es un módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo lógico o de traducción que tenga un encapsulado BQA, BQB, RGY, RSV, RJW o RHL de 14 a 24 pines.

Guía del usuario: PDF | HTML
No disponible en TI.com
Modelo de simulación

SN74LVTH125 Behavioral SPICE Model

SCBM115.ZIP (7 KB) - PSpice Model
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Modelo de simulación

SN74LVTH125 IBIS Model

SCEM176.ZIP (16 KB) - IBIS Model
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

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