SN74LVTH162241

Name: SN74LVTH162241
Brand: TI
SKU: SN74LVTH162241
Price: 0.455 USD

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Búferes de 16 canales, 2.7 V a 3.6 V con retención de bus, entradas CMOS compatibles con TTL y salid

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document-pdfAcrobat SN54LVTH162241, SN74LVTH162241 datasheet (Rev. E) (Inglés)

SN74LVTH162241

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Detalles del producto

Technology family

LVT

Supply voltage (min) (V)

2.7

Supply voltage (max) (V)

3.6

Number of channels

16

IOL (max) (mA)

12

Supply current (max) (µA)

5000

IOH (max) (mA)

-12

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LVT

Supply voltage (min) (V)

2.7

Supply voltage (max) (V)

3.6

Number of channels

16

IOL (max) (mA)

12

Supply current (max) (µA)

5000

IOH (max) (mA)

-12

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

48

164.358 mm² 15.88 x 10.35

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

Members of the Texas Instruments Widebus™ Family
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
I_off and Power-Up 3-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus is a trademark of Texas Instruments.

Members of the Texas Instruments Widebus™ Family
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
I_off and Power-Up 3-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus is a trademark of Texas Instruments.

These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide noninverting outputs and complementary output-enable (OE and OE) inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.

When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN54LVTH162241 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH162241 is characterized for operation from -40°C to 85°C.

These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide noninverting outputs and complementary output-enable (OE and OE) inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.

When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN54LVTH162241 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH162241 is characterized for operation from -40°C to 85°C.

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Documentación técnica

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Ver todo 17

	Tipo	Título	Fecha
*	Data sheet	SN54LVTH162241, SN74LVTH162241 datasheet (Rev. E)	01 nov 2006
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Application note	An Overview of Bus-Hold Circuit and the Applications (Rev. B)	17 sep 2018
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 may 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 may 2002
	Selection guide	Advanced Bus Interface Logic Selection Guide	09 ene 2001
	Application note	LVT-to-LVTH Conversion	08 dic 1998
	Application note	LVT Family Characteristics (Rev. A)	01 mar 1998
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 ago 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 may 1996

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