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DS99R101

最終購入段階

3 ～ 40MHz、DC 平衡型、24 ビット LVDS シリアライザ

ご注文はこちら
データシート

DS99R101

最終購入段階
データシート ご注文はこちら

製品詳細

Protocols Catalog Rating Catalog Operating temperature range (°C) 0 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) 0 to 70
TQFP (PFB) 48 81 mm² 9 x 9
  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with No External Coding Required
  • Individual Power-Down Controls for Both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS Inputs and Control Pins Have Internal Pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • 48-Pin TQFP Package
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range 0°C to +70°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with No External Coding Required
  • Individual Power-Down Controls for Both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS Inputs and Control Pins Have Internal Pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • 48-Pin TQFP Package
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range 0°C to +70°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R101/DS99R102 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R101/DS99R102 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer データシート (Rev. D) 2013年 4月 16日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点