ホーム インターフェイス その他のインターフェイス

SN54ACT8990

アクティブ

テスト バス コントローラ

製品詳細

Protocols JTAG Rating Military Operating temperature range (°C) -55 to 125
Protocols JTAG Rating Military Operating temperature range (°C) -55 to 125
CFP (HV) 68 156.7504 mm² 12.52 x 12.52 CPGA (GB) 68 594.3844 mm² 24.38 x 24.38
  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Control Operation of Up to Six Parallel Target Scan Paths
  • Accommodate Pipeline Delay to Target of Up to 31 Clock Cycles
  • Scan Data Up to 232 Clock Cycles
  • Execute Instructions for Up to 232 Clock Cycles
  • Each Device Includes Four Bidirectional Event Pins for Additional Test Capability
  • Inputs Are TTL-Voltage Compatible
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • Packaged in 44-Pin Plastic Leaded Chip Carrier (FN), 68-Pin Ceramic Pin Grid Array (GB), and 68-Pin Ceramic Quad Flat Packages (HV)

    SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Control Operation of Up to Six Parallel Target Scan Paths
  • Accommodate Pipeline Delay to Target of Up to 31 Clock Cycles
  • Scan Data Up to 232 Clock Cycles
  • Execute Instructions for Up to 232 Clock Cycles
  • Each Device Includes Four Bidirectional Event Pins for Additional Test Capability
  • Inputs Are TTL-Voltage Compatible
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • Packaged in 44-Pin Plastic Leaded Chip Carrier (FN), 68-Pin Ceramic Pin Grid Array (GB), and 68-Pin Ceramic Quad Flat Packages (HV)

    SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

The 'ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The 'ACT8990 differ from other SCOPETM integrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary-scannable devices.

The required signals of the JTAG serial-test bus - test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC can be configured to generate up to six separate TMS signals [TMS (5-0)], it can be used to control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO signals).

While most operations of the TBC are synchronous to TCKI, a test-off (TOFF\) input is provided for output control of the target interface, and a test-reset (TRST\) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (3-0)] I/Os are provided for asynchronous communication to target device(s). Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit counters.

The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus [ADRS (4-0)] and the 16-bit read/write data bus [DATA (15-0)]. Read (RD\) and write (WR\) strobes are implemented such that the critical host-interface timing is independent of the TCKI period. Any one of 24 registers can be addressed for read and/or write operations. In addition to control and status registers, the TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the host via ready (RDY\) and interrupt (INT\) outputs.

Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A 32-bit counter can be preset to allow a predetermined number of execution or scan operations.

Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO output is written by the host to the write buffer.

 

The SN54ACT8990 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8990 is characterized for operation from 0°C to 70°C.

 

 

 

 

 

NC - No internal connection

The 'ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The 'ACT8990 differ from other SCOPETM integrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary-scannable devices.

The required signals of the JTAG serial-test bus - test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC can be configured to generate up to six separate TMS signals [TMS (5-0)], it can be used to control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO signals).

While most operations of the TBC are synchronous to TCKI, a test-off (TOFF\) input is provided for output control of the target interface, and a test-reset (TRST\) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (3-0)] I/Os are provided for asynchronous communication to target device(s). Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit counters.

The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus [ADRS (4-0)] and the 16-bit read/write data bus [DATA (15-0)]. Read (RD\) and write (WR\) strobes are implemented such that the critical host-interface timing is independent of the TCKI period. Any one of 24 registers can be addressed for read and/or write operations. In addition to control and status registers, the TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the host via ready (RDY\) and interrupt (INT\) outputs.

Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A 32-bit counter can be preset to allow a predetermined number of execution or scan operations.

Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO output is written by the host to the write buffer.

 

The SN54ACT8990 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8990 is characterized for operation from 0°C to 70°C.

 

 

 

 

 

NC - No internal connection

ダウンロード 字幕付きのビデオを表示 ビデオ

技術資料

star =TI が選定したこの製品の主要ドキュメント
結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
13 をすべて表示
種類 タイトル 最新の英語版をダウンロード 日付
* データシート Test Bus Controllers, JTAG TAP Masters With 16-Bit Generic Host Interfaces データシート (Rev. E) 1997年 1月 1日
* SMD SN54ACT8990 SMD 5962-93228 2016年 6月 21日
アプリケーション・ノート Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
セレクション・ガイド Logic Guide (Rev. AB) 2017年 6月 12日
アプリケーション・ノート Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
セレクション・ガイド ロジック・ガイド (Rev. AA 翻訳版) 最新英語版 (Rev.AB) 2014年 11月 6日
ユーザー・ガイド LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
アプリケーション・ノート Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
アプリケーション・ノート Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
アプリケーション・ノート TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
アプリケーション・ノート CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
アプリケーション・ノート Designing With Logic (Rev. C) 1997年 6月 1日
アプリケーション・ノート Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

シミュレーション・ツール

PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®

PSpice® for TI は、各種アナログ回路の機能評価に役立つ、設計とシミュレーション向けの環境です。設計とシミュレーションに適したこのフル機能スイートは、Cadence® のアナログ分析エンジンを使用しています。PSpice for TI は無償で使用でき、アナログや電源に関する TI の製品ラインアップを対象とする、業界でも有数の大規模なモデル・ライブラリが付属しているほか、選択された一部のアナログ動作モデルも利用できます。

設計とシミュレーション向けの環境である PSpice for TI (...)
シミュレーション・ツール

TINA-TI — SPICE ベースのアナログ・シミュレーション・プログラム

TINA-TI は、DC 解析、過渡解析、周波数ドメイン解析など、SPICE の標準的な機能すべてを搭載しています。TINA には多彩な後処理機能があり、結果を必要なフォーマットにすることができます。仮想計測機能を使用すると、入力波形を選択し、回路ノードの電圧や波形を仮想的に測定することができます。TINA の回路キャプチャ機能は非常に直観的であり、「クイックスタート」を実現できます。

TINA-TI をインストールするには、約 500MB が必要です。インストールは簡単です。必要に応じてアンインストールも可能です。(そのようなことはないと思いますが)

TINA は DesignSoft (...)

ユーザー ガイド: PDF
英語版 (Rev.A): PDF
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
CFP (HV) 68 Ultra Librarian
CPGA (GB) 68 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

サポートとトレーニング

TI E2E™ フォーラムでは、TI のエンジニアからの技術サポートを提供

コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​

ビデオ