TFP201A
最大 112MHz の出力ピクセル レート対応、HSYNC ジッタへの対処機能搭載、不具合を修正したエラッタ製品、Panelbus DVI レシーバ
TFP201A
- Supports SXGA Resolution (Output Pixel Rates Up to 112 MHz)
- Digital Visual Interface (DVI) Specification Compliant1
- True-Color, 24 Bit/Pixel, 16.7M Colors at 1 or 2-Pixels Per Clock
- Laser Trimmed Internal Termination Resistors for Optimum Fixed Impedance Matching
- Skew Tolerant Up to One Pixel Clock Cycle
- 4x Over-Sampling
- Reduced Power Consumption \x96 1.8 V Core Operation With 3.3 V I/Os and Supplies2
- Reduced Ground Bounce Using Time Staggered Pixel Outputs
- Lowest Noise and Best Power Dissipation Using TI PowerPAD™ Packaging
- Advanced Technology Using TI 0.18-um EPIC-5™ CMOS Process
- TFP201A Incorporates HSYNC Jitter Immunity3
- The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays The TFP201 and TFP201A are compliant to the DVI Specification Rev. 1.0.
- The TFP201/201A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies.
- The TFP201A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal.
PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments.
I2C is a licensed bus protocol from Phillips Semiconductor, Inc.
The Texas Instruments TFP201 and TFP201A are TI PanelBus flat panel display products, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP201/201A finds applications in any design requiring high-speed digital interface.
The TFP201/201A supports display resolutions up to SXGA in 24-bit true color pixel format. The TFP201/201Ab offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time staggered pixel outputs for reduced ground bounce.
PowerPAD advanced packaging technology results in best of class power dissipation, footprint, and ultra-low ground inductance.
The TFP201/201A combines PanelBus circuit innovation with TI\x92s advanced 0.18-mm EPIC-5E CMOS process technology, along with TI PowerPAD package technology to achieve a reliable, low-powered, low noise, high-speed digital interface solution.
技術資料
種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
---|---|---|---|---|---|---|
* | エラッタ | TFP101(A), TFP201(A), TFP401(A) Errata | 2003年 11月 11日 | |||
* | エラッタ | TFP101/A, TFP201/A, TFP401/A, TFP403 Data Sheet Errata | 2003年 6月 27日 | |||
* | データシート | TI PanelBus(TM) Digital Receiver データシート (Rev. A) | 2002年 5月 21日 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点