TL16C2552

Name: TL16C2552
Brand: TI
SKU: TL16C2552
Price: 3.353 USD

アクティブ

1.8V ～ 5V、デュアル UART、16 バイト FIFO 付

ご注文はこちら

データシート

document-pdfAcrobat 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS データシート (Rev. A) (英語)

TL16C2552

アクティブ

データシート

ご注文はこちら

製品詳細

Number of channels

2

FIFO (Byte)

16

Rx FIFO trigger levels (#)

4

Programmable FIFO trigger levels

No

CPU interface

X86

Baud rate at Vcc = 2.5 V & with 16x sampling (max) (Mbps)

1

Baud rate at Vcc = 1.8 V & with 16x sampling (max) (Mbps)

0.625

Baud rate at Vcc = 3.3 V & with 16x sampling (max) (Mbps)

1.25

Baud rate at Vcc = 5 V & with 16x sampling (max) (Mbps)

1.5

Operating voltage (V)

1.8, 2.5, 3.3, 5

Auto RTS/CTS

Yes

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Number of channels

2

FIFO (Byte)

16

Rx FIFO trigger levels (#)

4

Programmable FIFO trigger levels

No

CPU interface

X86

Baud rate at Vcc = 2.5 V & with 16x sampling (max) (Mbps)

1

Baud rate at Vcc = 1.8 V & with 16x sampling (max) (Mbps)

0.625

Baud rate at Vcc = 3.3 V & with 16x sampling (max) (Mbps)

1.25

Baud rate at Vcc = 5 V & with 16x sampling (max) (Mbps)

1.5

Operating voltage (V)

1.8, 2.5, 3.3, 5

Auto RTS/CTS

Yes

Rating

Catalog

Operating temperature range (°C)

-40 to 85

PLCC (FN)

44

307.3009 mm² 17.53 x 17.53

Programmable Auto-RTS and Auto-CTS
In Auto-CTS Mode, CTS Controls the Transmitter
In Auto-RTS Mode, RCV FIFO Contents, and Threshold Control RTS
Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment is on the Same Power Drop
Capable of Running With All Existing TL16C450 Software
After Reset, All Registers Are Identical to the TL16C450 Register Set
Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With V_CC = 5 V
Up to 20-MHz Clock Rate for up to 1.25-Mbaud Operation With V_CC = 3.3 V
Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With V_CC = 2.5 V
Up to 10-MHz Clock Rate for up to 625-kbaud Operation With V_CC = 1.8 V
In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (2¹⁶ - 1) and Generates an Internal 16 × Clock
Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
5-V, 3.3-V, 2.5-V, and 1.8 V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
Fully Programmable Serial Interface Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation and Detection
- 1-, 1 ½, or 2-Stop Bit Generation
- Baud Generation (dc to 1 Mbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities:
- Loopback Controls for Communications Link Fault Isolation
- Break, Parity, Overrun, and Framing Error Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)
Available in 44-Pin PLCC (FN) or 32-Pin QFN (RHB) Packages
Each UART's Internal Register Set May Be Written Concurrently to Save Setup Time
Multi-Function Output (MF) Allows Users to Select Among Several Functions, Saving Package Pins
APPLICATIONS
- Point-of-Sale Terminals
- Gaming Terminals
- Portable Applications
- Router Control
- Cellular Data
- Factory Automation

Programmable Auto-RTS and Auto-CTS
In Auto-CTS Mode, CTS Controls the Transmitter
In Auto-RTS Mode, RCV FIFO Contents, and Threshold Control RTS
Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment is on the Same Power Drop
Capable of Running With All Existing TL16C450 Software
After Reset, All Registers Are Identical to the TL16C450 Register Set
Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With V_CC = 5 V
Up to 20-MHz Clock Rate for up to 1.25-Mbaud Operation With V_CC = 3.3 V
Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With V_CC = 2.5 V
Up to 10-MHz Clock Rate for up to 625-kbaud Operation With V_CC = 1.8 V
In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (2¹⁶ - 1) and Generates an Internal 16 × Clock
Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
5-V, 3.3-V, 2.5-V, and 1.8 V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
Fully Programmable Serial Interface Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation and Detection
- 1-, 1 ½, or 2-Stop Bit Generation
- Baud Generation (dc to 1 Mbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities:
- Loopback Controls for Communications Link Fault Isolation
- Break, Parity, Overrun, and Framing Error Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)
Available in 44-Pin PLCC (FN) or 32-Pin QFN (RHB) Packages
Each UART's Internal Register Set May Be Written Concurrently to Save Setup Time
Multi-Function Output (MF) Allows Users to Select Among Several Functions, Saving Package Pins
APPLICATIONS
- Point-of-Sale Terminals
- Gaming Terminals
- Portable Applications
- Router Control
- Cellular Data
- Factory Automation

The TL16C2552 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two TL16C550D UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2552.

Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, a selectable autoflow control feature can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input, thus eliminating overruns in the receive FIFO.

Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt system that can be tailored to the application.

Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of from 1 to 65535, thus producing a 16× internal reference clock for the transmitter and receiver logic. Each ACE accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at 24 MHz.

Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.

The TL16C2552 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two TL16C550D UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2552.

Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, a selectable autoflow control feature can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input, thus eliminating overruns in the receive FIFO.

Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt system that can be tailored to the application.

Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of from 1 to 65535, thus producing a 16× internal reference clock for the transmitter and receiver logic. Each ACE accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at 24 MHz.

Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.

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