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TLK2501

アクティブ

1.5 ~ 2.5Gbps トランシーバ

製品詳細

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
HVQFP (RCP) 64 144 mm² 12 x 12
  • Hot-Plug Protection
  • 1.5 to 2.5 Gigabits Per Second (Gbps) Serializer/Deserializer
  • High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD™)
  • 2.5-V Power Supply for Low Power Operation
  • Programmable Voltage Output Swing on Serial Output
  • Interfaces to Backplane, Copper Cables, or Optical Converters
  • Rated for Industrial Temperature Range
  • On-Chip 8-Bit/10-Bit (8B/10B) Encoding/Decoding, Comma Alignment, and Link Synchronization
  • On-Chip PLL Provides Clock Synthesis From Low-Speed Reference
  • Receiver Differential Input Thresholds 200 mV Minimum
  • Typical Power: 360 mW
  • Loss of Signal (LOS) Detection
  • Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link

PowerPAD is a trademark of Texas Instruments.

  • Hot-Plug Protection
  • 1.5 to 2.5 Gigabits Per Second (Gbps) Serializer/Deserializer
  • High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD™)
  • 2.5-V Power Supply for Low Power Operation
  • Programmable Voltage Output Swing on Serial Output
  • Interfaces to Backplane, Copper Cables, or Optical Converters
  • Rated for Industrial Temperature Range
  • On-Chip 8-Bit/10-Bit (8B/10B) Encoding/Decoding, Comma Alignment, and Link Synchronization
  • On-Chip PLL Provides Clock Synthesis From Low-Speed Reference
  • Receiver Differential Input Thresholds 200 mV Minimum
  • Typical Power: 360 mW
  • Loss of Signal (LOS) Detection
  • Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link

PowerPAD is a trademark of Texas Instruments.

The TLK2501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK2501 supports an effective serial interface speed of 1.5 Gbps to 2.5 Gbps, providing up to 2 Gbps of data bandwidth. The TLK2501 is pin-for-pin compatible with the TLK2500. The TLK2501 is both pin-for-pin compatible with and functionally identical to the TLK1501, a 0.6 to 1.5 Gbps transceiver, and the TLK3101, a 2.5 to 3.125 Gbps transceiver, providing a wide range of performance solutions with no required board layout changes.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 . The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future.

The TLK2501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 2.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 1.20 Gbps to 2.0 Gbps (16 bits data x the GTX_CLK frequency).

The TLK2501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which has an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK2501 PowerPAD is soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board.

The TLK2501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface.

The TLK2501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. This circuit also holds the parallel side output signal terminals as well as DOUTTXP and DOUTTXN in a high-impedance state during power up.

The TLK2501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.

To prevent a data bit error from causing a data packet from being interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK2501.

The TLK2501 allows users to implement redundant ports by connecting receive data bus terminals from two TLK2501 devices together. Asserting the LCKREFN to go to a low state causes the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a ransmit-only mode since the receiver is not tracking the data.

The TLK2501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power-efficient, consuming less than 360 mW typically. The TLK2501 is characterized for operation from –40°C to 85°C.

The TLK2501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK2501 supports an effective serial interface speed of 1.5 Gbps to 2.5 Gbps, providing up to 2 Gbps of data bandwidth. The TLK2501 is pin-for-pin compatible with the TLK2500. The TLK2501 is both pin-for-pin compatible with and functionally identical to the TLK1501, a 0.6 to 1.5 Gbps transceiver, and the TLK3101, a 2.5 to 3.125 Gbps transceiver, providing a wide range of performance solutions with no required board layout changes.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 . The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future.

The TLK2501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 2.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 1.20 Gbps to 2.0 Gbps (16 bits data x the GTX_CLK frequency).

The TLK2501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which has an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK2501 PowerPAD is soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board.

The TLK2501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface.

The TLK2501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. This circuit also holds the parallel side output signal terminals as well as DOUTTXP and DOUTTXN in a high-impedance state during power up.

The TLK2501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.

To prevent a data bit error from causing a data packet from being interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK2501.

The TLK2501 allows users to implement redundant ports by connecting receive data bus terminals from two TLK2501 devices together. Asserting the LCKREFN to go to a low state causes the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a ransmit-only mode since the receiver is not tracking the data.

The TLK2501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power-efficient, consuming less than 360 mW typically. The TLK2501 is characterized for operation from –40°C to 85°C.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート 1.5 to 2.5 Gbps Transceiver データシート (Rev. D) 2003年 6月 27日
アプリケーション・ノート Using TI's CDCV304 w/Backplane Transceiver (TLK1201/1501/2201/2501/2701/3101) (Rev. A) 2006年 4月 20日
アプリケーション・ノート Interfacing Between LVPECL, VML, CML and LVDS Levels 2002年 12月 17日
EVM ユーザー ガイド (英語) TLK2501 Serdes EVM Kit Setup and Usage 2000年 9月 12日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価ボード

TLK2501EVM — TLK2501 シリアライザ/デシリアライザ評価モジュール

The TLK2501 serdes evaluation module (EVM) board is used to evaluate the TLK2501 device (VQFP) and associated optical interface (NetLight™) for point-to-point data transmission applications.

The board enables the designer to connect 50 ohm parallel buses to both transmiter and receiver connectors. (...)

ユーザー ガイド: PDF
シミュレーション・ツール

PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®

PSpice® for TI は、各種アナログ回路の機能評価に役立つ、設計とシミュレーション向けの環境です。設計とシミュレーションに適したこのフル機能スイートは、Cadence® のアナログ分析エンジンを使用しています。PSpice for TI は無償で使用でき、アナログや電源に関する TI の製品ラインアップを対象とする、業界でも有数の大規模なモデル・ライブラリが付属しているほか、選択された一部のアナログ動作モデルも利用できます。

設計とシミュレーション向けの環境である PSpice for TI (...)
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TINA-TI — SPICE ベースのアナログ・シミュレーション・プログラム

TINA-TI は、DC 解析、過渡解析、周波数ドメイン解析など、SPICE の標準的な機能すべてを搭載しています。TINA には多彩な後処理機能があり、結果を必要なフォーマットにすることができます。仮想計測機能を使用すると、入力波形を選択し、回路ノードの電圧や波形を仮想的に測定することができます。TINA の回路キャプチャ機能は非常に直観的であり、「クイックスタート」を実現できます。

TINA-TI をインストールするには、約 500MB が必要です。インストールは簡単です。必要に応じてアンインストールも可能です。(そのようなことはないと思いますが)

TINA は DesignSoft (...)

ユーザー ガイド: PDF
英語版 (Rev.A): PDF
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
HVQFP (RCP) 64 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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