CDC3S04

Name: CDC3S04
Brand: TI
SKU: CDC3S04
Price: 1.346 USD

활성

LDO를 지원하는 쿼드 사인파 클록 버퍼

지금 주문

데이터 시트

document-pdfAcrobat CDC3S04 Quad Sine-Wave Clock Buffer with LDO. datasheet (Rev. C) (영어)

CDC3S04

활성

데이터 시트

지금 주문

제품 상세 정보

Function

Single-ended

Additive RMS jitter (typ) (fs)

300

Output frequency (max) (MHz)

52

Number of outputs

4

Output supply voltage (V)

1.8

Core supply voltage (V)

1.8

Output skew (ps)

50

Features

SINE wave

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

SINE

Input type

SINE

Function

Single-ended

Additive RMS jitter (typ) (fs)

300

Output frequency (max) (MHz)

52

Number of outputs

4

Output supply voltage (V)

1.8

Core supply voltage (V)

1.8

Output skew (ps)

50

Features

SINE wave

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

SINE

Input type

SINE

DSBGA (YFF)

20

3.96 mm² 1.8 x 2.2

1:4 Low-Jitter Clock Buffer
Single-Ended Sine-Wave Clock Input and Outputs
Ultralow Phase Noise and Standby Current
Individual Clock Request Inputs for Each Output
On-Chip Low-Dropout Output (LDO) for Low-Noise TCXO Supply
Serial I²C Interface (Compatible With High-Speed Mode,
3.4 Mbit/s)
1.8-V Device Power Supply
Wide Temperature Range, –40°C to 85°C
ESD Protection: 2 KV HBM, 750 V CDM, and 100 V MM
Small 20-Pin Chip-Scale Package: 0.4-mm Pitch WCSP (1.6 mm × 2 mm)

1:4 Low-Jitter Clock Buffer
Single-Ended Sine-Wave Clock Input and Outputs
Ultralow Phase Noise and Standby Current
Individual Clock Request Inputs for Each Output
On-Chip Low-Dropout Output (LDO) for Low-Noise TCXO Supply
Serial I²C Interface (Compatible With High-Speed Mode,
3.4 Mbit/s)
1.8-V Device Power Supply
Wide Temperature Range, –40°C to 85°C
ESD Protection: 2 KV HBM, 750 V CDM, and 100 V MM
Small 20-Pin Chip-Scale Package: 0.4-mm Pitch WCSP (1.6 mm × 2 mm)

The CDC3S04 is a four-channel low-power low-jitter sine-wave clock buffer. It can be used to buffer a single master clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter.

Each output has its own clock request inputs which enables the dedicated clock output. These clock requests are active-high (can also be changed to be active-low via I²C), and an output signal is generated that can be sent back to the master clock to request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND or push-pull functionality via I²C.

The CDC3S04 also provides an I²C interface (Hs-mode) that can be used to enable or disable the outputs, select the polarity of the REQ inputs, and allow control of internal decoding.

The CDC3S04 features an on-chip high-performance LDO that accepts voltages from 2.3 V to 5.5 V and outputs a 1.8-V supply. This 1.8-V supply can be used to power an external 1.8-V TCXO. It can be enabled or disabled for power saving at the TCXO.

A low signal at the RESET input switches the outputs CLK1 and CLK4 into the default state. In this configuration, CLK1 and CLK4 are ON (see ); the remaining device function is not affected. Also, the RESET input provides a glitch filter which rejects spikes of typical 300 ns on the RESET line to preserve false reset. A complete device reset to the default condition can be initiated by a power-up cycle of V_{DD_DIG}.

The CDC3S04 operates from two 1.8-V supplies. There is a core supply (VDD_DIG/GND_DIG) for the core logic and a low-noise analog supply (VDD_ANA/GND_ANA) for the sine-wave outputs. The CDC3S04 is designed for sequence-less power up. Both supply voltages may be applied in any order.

The CDC3S04 is offered in a 0.4-mm pitch WCSP package (1.6 mm × 2 mm) and is optimized for low standby current (0.5 µA). It is characterized for operation from –40°C to 85°C.

The CDC3S04 is a four-channel low-power low-jitter sine-wave clock buffer. It can be used to buffer a single master clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter.

Each output has its own clock request inputs which enables the dedicated clock output. These clock requests are active-high (can also be changed to be active-low via I²C), and an output signal is generated that can be sent back to the master clock to request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND or push-pull functionality via I²C.

The CDC3S04 also provides an I²C interface (Hs-mode) that can be used to enable or disable the outputs, select the polarity of the REQ inputs, and allow control of internal decoding.

The CDC3S04 features an on-chip high-performance LDO that accepts voltages from 2.3 V to 5.5 V and outputs a 1.8-V supply. This 1.8-V supply can be used to power an external 1.8-V TCXO. It can be enabled or disabled for power saving at the TCXO.

A low signal at the RESET input switches the outputs CLK1 and CLK4 into the default state. In this configuration, CLK1 and CLK4 are ON (see ); the remaining device function is not affected. Also, the RESET input provides a glitch filter which rejects spikes of typical 300 ns on the RESET line to preserve false reset. A complete device reset to the default condition can be initiated by a power-up cycle of V_{DD_DIG}.

The CDC3S04 operates from two 1.8-V supplies. There is a core supply (VDD_DIG/GND_DIG) for the core logic and a low-noise analog supply (VDD_ANA/GND_ANA) for the sine-wave outputs. The CDC3S04 is designed for sequence-less power up. Both supply voltages may be applied in any order.

The CDC3S04 is offered in a 0.4-mm pitch WCSP package (1.6 mm × 2 mm) and is optimized for low standby current (0.5 µA). It is characterized for operation from –40°C to 85°C.

filter

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4개 모두 보기

	유형	직함	날짜
*	Data sheet	CDC3S04 Quad Sine-Wave Clock Buffer with LDO. datasheet (Rev. C)	2012/07/25
	Application note	Power Supply Rejection to Noise in Sinusoidal Clock Buffers: CDC3S04 (Rev. A)	2010/06/21
	Application note	Using the CDC3S04	2010/04/18
	User guide	Quad Sine-Wave Clock Buffer Evaluation Board	2010/03/08

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

CDC3S04EVM — CDC3S04EVM 평가 모듈

CDC3S04는 4채널 저전력 사인파 클록 버퍼입니다. 단일 마스터 클록을 여러 주변 장치에 버퍼링하는 데 사용할 수 있습니다. 4개의 사인파 출력(CLK1 – CLK4)은 최소 채널 간 스큐 및 초저 가산 출력 지터를 위해 설계되었습니다. 각 출력에는 전용 클록 출력을 가능하게 하는 자체 클록 요청 입력이 있습니다. 이러한 클록 요청은 액티브 하이(I2C를 통해 액티브-로우로 변경할 수도 있음)이며, 출력 신호가 생성되어 클록(MCLK_REQ)을 요청할 수 있습니다. MCKL_REQ는 오픈 소스 출력이며 유선-OR 기능(기본 (...)

사용 설명서: PDF

TI.com에서 구매 불가

시뮬레이션 모델

CDC3S04 IBIS Model (Rev. A)

SLLM072A.ZIP (63 KB) - IBIS Model

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Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)

요청

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DSBGA (YFF)	20	Ultra Librarian

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CDC3S04

LDO를 지원하는 쿼드 사인파 클록 버퍼

CDC3S04

제품 상세 정보

기술 자료

설계 및 개발

CDC3S04EVM — CDC3S04EVM 평가 모듈

CDC3S04 IBIS Model (Rev. A)

CLOCK-TREE-ARCHITECT — 클록 트리 아키텍트 프로그래밍 소프트웨어

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

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