TLC555
- Very low power consumption:
- 1-mW typical at V DD = 5 V
- Capable of operation in astable mode
- CMOS output capable of swinging rail to rail
- High output current capability
- Sink: 100-mA typical
- Source: 10-mA typical
- Output fully compatible with CMOS, TTL, and MOS
- Low supply current reduces spikes during output transitions
- Single-supply operation from 2 V to 15 V
- Functionally interchangeable with the NE555; has same pinout
- ESD protection exceeds 1000 V per ANSI/ESDA/JEDEC JS-001
- Available in Q-temp automotive
- High-reliability automotive applications
- Configuration control and print support
- Qualification to automotive standards
The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of a high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.
Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | TLC555 LinCMOS™ Technology Timer datasheet (Rev. J) | PDF | HTML | 2023/11/27 |
Circuit design | Frequency-to-Voltage Conversion Circuit Using a 555 Timer | 2023/09/21 | ||
Application note | Considering TI Smart DACs As an Alternative to 555 Timers | PDF | HTML | 2021/09/02 | |
More literature | Design low-duty-cycle timer circuits | 2016/10/03 | ||
Application note | TLC555-Q1 Used as a Positive and Negative Charge Pump | 2016/05/25 | ||
Application note | Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers | 2011/09/13 |
설계 및 개발
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TLC555 TINA-TI Astable Reference Design (Rev. B)
TLC555 TINA-TI Mono Reference Design (Rev. B)
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패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
PDIP (P) | 8 | Ultra Librarian |
SOIC (D) | 8 | Ultra Librarian |
SOP (PS) | 8 | Ultra Librarian |
TSSOP (PW) | 14 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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