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Arm 式處理器

DRA746

現行

具圖形與 DSP 且適用車載資訊娛樂系統與儀錶板的雙 1.5 GHz Arm Cortex-A15 SoC 處理器

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勘誤表

DRA746

現行
產品規格表 立即訂購

產品詳細資料

Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1500 Coprocessors 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 1 PCIe Gen 2 Hardware accelerators 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection TI functional safety category Functional Safety-Compliant Rating Automotive Operating temperature range (°C) to
Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1500 Coprocessors 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 1 PCIe Gen 2 Hardware accelerators 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection TI functional safety category Functional Safety-Compliant Rating Automotive Operating temperature range (°C) to
FCBGA (ABC) 760 529 mm² 23 x 23
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.
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類型 標題 日期
* Data sheet DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 datasheet (Rev. F) PDF | HTML 2019年 5月 7日
* Errata DRA75x, DRA74x Silicon Errata Automotive Infotainment Silicon Revision 2.0, 1.1 (Rev. K) PDF | HTML 2024年 9月 8日
* User guide DRA75x, DRA74x Technical Reference Manual (SR2.0 & SR1.1) (Rev. H) PDF | HTML 2024年 5月 24日
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021年 5月 5日
More literature Building your application with security in mind (Rev. E) 2020年 10月 28日
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020年 8月 24日
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020年 1月 6日
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019年 6月 11日
Application note Achieving Early CAN Response on DRA7xx Devices 2018年 11月 28日
Application note DRA74x_75x/DRA72x Performance (Rev. A) 2018年 10月 31日
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 2018年 9月 14日
Application note The Implementation of YUV422 Output for SRV 2018年 8月 2日
Application note MMC DLL Tuning (Rev. B) 2018年 7月 31日
Application note Integrating AUTOSAR on TI SoC: Fundamentals 2018年 6月 18日
Application note ECC/EDC on TDAxx (Rev. B) 2018年 6月 13日
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem 2018年 6月 12日
Application note Sharing VPE Between VISIONSDK and PSDKLA 2018年 5月 4日
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) 2018年 2月 13日
Technical article Jacinto™ DRA automotive processors drive digital cockpit solutions PDF | HTML 2018年 1月 12日
Application note Flashing Utility - mflash 2018年 1月 9日
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 2017年 11月 30日
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 2017年 11月 27日
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017年 11月 7日
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017年 11月 3日
Application note Robust Rear-View Camera (RVC) App Report 2017年 9月 13日
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017年 9月 12日
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 2017年 8月 14日
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 2017年 7月 12日
White paper Revolutionize the automotive cockpit 2017年 6月 2日
Application note Linux Boot Time Optimizations on DRA7xx Devices 2017年 3月 31日
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 2017年 2月 17日
Application note Early Splash Screen on DRA7x Devices 2017年 1月 31日
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016年 12月 15日
Application note Gstreamer Migration Guidelines 2016年 4月 26日
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide 2016年 4月 21日
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide 2016年 4月 21日
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU 2016年 4月 14日
Application note Tools and Techniques for Audio Debugging 2016年 4月 13日
Application note Debugging Tools and Techniques With IPC3.x 2016年 3月 30日
Technical article Infotainment for the Masses – Volkswagen MIB II Standard powered by TI PDF | HTML 2016年 2月 17日
EVM User's guide DRA75x and DRA74x EVM CPU Board User's Guide 2016年 2月 9日
User guide JAMR3 Tuner Application Board User’s Guide 2016年 2月 9日
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 2016年 1月 15日
Technical article Difficult to see. Always in motion is the future PDF | HTML 2016年 1月 4日
Technical article Securing the Scene PDF | HTML 2015年 12月 16日
Technical article What a journey: from Archimedes to reconfigurable clusters PDF | HTML 2015年 11月 23日
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 2014年 10月 14日
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014年 8月 13日

設計與開發

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開發板

J6EVM5777 — DRA7xx 評估模組

The Jacinto™ DRA7xx evaluation module platform designed to speed up development efforts and reduce time to market for applications such as infotainment, reconfigurable digital cluster or integrated digital cockpit. To allow scalability and re-use across DRA74x and DRA75x Jacinto (...)

從：SVTRONICS INC
使用指南: PDF
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開發板

J6PEVM577P — DRA7xP 評估模組

The DRA77xP/DRA76xP-ACD is an evaluation platform designed to allow scalability and re-use across DRA77xP and DRA76xP JacintoTM Infotainment System-on-Chips (SoCs), it is based on Jacinto DRA77xP SoC that incorporates a heterogeneous, scalable architecture that includes a mix of two ARM Cortex-A15 (...)

從：SVTRONICS INC
使用指南: PDF
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

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產品
Arm 式處理器
DRA710 — 適用於資訊娛樂系統與儀錶板，且含繪圖的 600 MHz ARM Cortex-A15 SoC 處理器 DRA712 — 適用車載資訊娛樂系統與儀錶板，且含圖形與雙 Arm Cortex-M4 的 600 MHz ARM Cortex-A15 SoC 處理器 DRA714 — 適用於資訊娛樂系統與儀錶板，且含繪圖和 DSP 的 600MHz ARM Cortex-A15 SoC 處理器 DRA716 — 適用於資訊娛樂系統與儀錶板，且含繪圖和 DSP 的 800 MHz ARM Cortex-A15 SoC 處理器 DRA718 — 適用於資訊娛樂系統與儀錶板，且含繪圖和 DSP 的 1 GHz ARM Cortex-A15 SoC 處理器 DRA722 — 適用於車載資訊娛樂系統與儀錶板，且含圖形與 DSP 的 800MHz Arm Cortex-A15 SoC 處理器 DRA724 — 適用於車載資訊娛樂系統與儀錶板，且含圖形與 DSP 的 1GHz ARM Cortex-A15 SoC 處理器 DRA725 — 適用於車載資訊娛樂系統與儀錶板，且含圖形與 DSP 的 1.2 GHz Arm Cortex-A15 SoC 處理器 DRA726 — 適用於車載資訊娛樂系統與儀錶板且具有圖形與 DSP 的 1.5 GHz Arm Cortex-A15 DRA746 — 具圖形與 DSP 且適用車載資訊娛樂系統與儀錶板的雙 1.5 GHz Arm Cortex-A15 SoC 處理器 DRA74P — 具有 ISP 並與 DRA74x SoC 處理器針腳相容的多核心 SoC 處理器 DRA756 — 適用於車載資通訊系統的雙 1.5 GHz A15、雙 EVE、雙 DSP、延伸週邊設備 SoC 處理器 DRA75P — 適用於資訊娛樂系統應用、具有 ISP 並與 DRA75x SoC 針腳相容的多核心 SoC 處理器 DRA76P — 適用於數位駕駛艙應用並具有 ISP 的高效能多核心 SoC 處理器 DRA77P — 適用於數位駕駛艙應用並具有延伸周邊設備和 ISP 的高效能多核心 SoC DRA790 — 適用於音訊放大器且具有 500 MHz C66x DSP 的 300 MHz ARM Cortex-A15 SoC 處理器 DRA791 — 適用於音訊放大器且具有 750 MHz C66x DSP 的 300 MHz ARM Cortex-A15 SoC 處理器 DRA793 — 適用於音訊放大器且具有 750 MHz C66x DSP 的 500 MHz ARM Cortex-A15 SoC 處理器 DRA797 — 適用於音訊放大器且具有 750 MHz C66x DSP 的 800 MHz ARM Cortex-A15 SoC 處理器
數位訊號處理器 (DSP)
DRA780 — 適用於音訊放大器且具有 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA781 — 適用於音訊放大器且具有 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA782 — 適用於音訊放大器且具有 2 個 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA783 — 適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA785 — 適用於音訊放大器且具有 2 個 1000 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 的 SoC 處理器 DRA786 — 適用於音訊放大器且具有 2 個 500 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器 DRA787 — 適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器 DRA788 — 適用於音訊放大器，且具有 2 個 1000 MHz C66x DSP 和 1 個 EVE 及 2 個雙 Arm Cortex-M4 的 SoC 處理器
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

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作業系統 (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
從：Green Hills Software
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模擬型號

DRA75x and DRA74x BSDL Model

SPRM667.ZIP (14 KB) - BSDL Model
下載
模擬型號

DRA75x and DRA74x IBIS Model

SPRM668.ZIP (18366 KB) - IBIS Model
下載
模擬型號

DRA75x and DRA74x Thermal Model

SPRM669.ZIP (2 KB) - Thermal Model
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ABC) 760 Ultra Librarian
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