Active antenna system mMIMO (AAS)

Products and reference designs

Active antenna system mMIMO (AAS)

Block diagram

Overview

Our integrated circuits and reference designs help you create active antenna systems (AAS) that enable massive MIMO (mMIMO) and beamforming with higher bandwidth and better system reliability. Our analog front end devices use a new RF sampling architecture, while our companion power and clocking technologies allow you to complete your 5G design with confidence.

Design requirements

Modern active antenna systems mMIMO require:

  • Reduced signal chain size and complexity while offering wide bandwidth and multi-frequency.
  • High-density power management operating at high ambient temperature.
  • Network synchronization over packet-based fronthaul interface.

Explore applications similar in function and design

Block diagram

Find products and reference designs for your system.

AAS RF Sampling (Sub 6 GHz)

Clocking Clocking TCXO/OCXO TCXO/OCXO Network synchronizer/ jitter cleaner Network synchronizer/jitter cleaner Clock buffer Clock buffer eCPRI eCPRI COM Port COM Port Fan / AC Fan / AC BBU eCPRI BBUeCPRI GPS Clock GPS Clock Communication Communication RS-485 RS-485 RS-232 RS-232 Ethernet PHY Ethernet PHY Memory Memory DDR DDR Flash Flash RF sampling analog front end RF sampling analog front end AFE AFE AFE AFE AFE AFE AFE AFE Antenna array Antenna array Power amplifier (PA) power Power amplifier (PA) power DC/DC controller DC/DC controller FET FET DC/DC converter DC/DC converter LDO LDO Point of load (POL) power Point of load (POL) power DC/DC controller DC/DC controller FET FET DC/DC converter DC/DC converter LDO LDO Sequencer Sequencer Analog front end (AFE) power Analog front end (AFE) power DC/DC converter DC/DC converter Load switch Load switch LDO LDO Multi-channel converter Multi-channel converter Multi-channel LDO Multi-channel LDO Isolated -48V DC/DC power supply Isolated -48V DC/DC power supply PWM controller PWM controller High/low side driver High/low side driver FET FET FET FET SyncFET driver SyncFET driver Isolated driver Isolated driver Aux bias supply Aux bias supply Digital isolator Digital isolator Voltage reference Voltage reference Current sense Current sense Glue logic Glue logic Voltage translation Voltage translation I/O expander I/O expander Logic gates Logic gates Supervisor & reset control Supervisor & reset control Optical Optical Current limit switch Current limit switch Retimer Retimer Front port controller Front port controller Optical module Optical module Digital baseband processor Digital baseband processor ASIC / FPGA ASIC / FPGA ARM ARM ASIC / FPGA ASIC / FPGA ASIC / FPGA ASIC / FPGA ASIC / FPGA ASIC / FPGA Digital front end (DFE) Digital front end (DFE) ASIC / FPGA ASIC / FPGA Retimer Retimer Protection Protection Hot swap controller Hot swap controller Driver Driver FET FET FET FET RF front end and power amplifier RF front end and power amplifier PA Module PA Module Filter Filter Filter Filter LNA LNA Duplexer Duplexer OPA OPA eFuse eFuse Current sense Current sense Analog monitor & control Analog monitor & control Temp sense Temp sense Switch Switch Filter Filter DVGA DVGA DVGA DVGA

Clocking

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Clock and Timing Circuitry that provides the ability to offer time and frequency synchronization over the packet based fronthaul interface (eCPRI) and also provide high frequency, low phase noise sampling clocks to the entire system. These signals can be challenging to generate and to route across the board, therefore clock buffers are used to distribute the clock signals with low skew.

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Clocks & timing (10)
Clock buffers
  • LMK1D2102LLow additive jitter LVDS buffer
    Data sheet: PDF | HTML
  • LMK1D2104LDual bank 4-channel output LVDS 1.8V, 2.5V, and 3.3V buffer with 0.7V output common mode option
    Data sheet: PDF | HTML
  • LMK1D2102Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer
    Data sheet: PDF | HTML
  • LMK1D1208P8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control
    Data sheet: PDF | HTML
  • CDCL1810A1.8-V 1-to-10 high performance differential clock buffer with individual output enable/disable
    Data sheet: PDF | HTML
  • LMK003344-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator
    Data sheet: PDF | HTML
Clock jitter cleaners
  • LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.
    Data sheet: PDF | HTML
  • LMK04806Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO
    Data sheet: PDF | HTML
  • LMK04803Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO
    Data sheet: PDF | HTML
  • LMK04832Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop
    Data sheet: PDF | HTML
RF & microwave (4)
RF PLLs & synthesizers
  • LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support
    Data sheet: PDF | HTML
  • LMX282022.6-GHz wideband RF synthesizer with phase synchronization, JESD and <5-µs frequency calibration
    Data sheet: PDF | HTML
  • LMX25813.76-GHz wideband frequency synthesizer with integrated VCO
    Data sheet: PDF | HTML
  • LMX25825.5-GHz high performance, wideband PLLatinum RF synthesizer
    Data sheet: PDF | HTML
  • TIDA-01016Clocking Reference Design for RF Sampling ADCs in Signal Analyzers and Wireless Testers
    Design guide: PDF Schematic: PDF
  • TIDA-01021Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
    Design guide: PDF Schematic: PDF Schematic: PDF
  • TIDA-01022Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
    Design guide: PDF | HTML Schematic: PDF
  • TIDA-01023High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
    Design guide: PDF Schematic: PDF Schematic: PDF
  • TIDA-010230Multi-channel RF transceiver, low-noise clocking reference design for radar and EW applications
    Design guide: PDF | HTML Schematic: PDF
  • TIDA-01024High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
    Design guide: PDF Schematic: PDF Schematic: PDF

Technical documentation

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Type Title Date
Technical article Are you ready for BAW? PDF | HTML 29 Jun 2023
Application note Protecting Radio, Baseband and Active Antenna Systems with TPS2352x Hot Swaps 24 Aug 2018
White paper 準備好迎接 5G 世界: 使用技術與硬體需求概論 22 Feb 2019
White paper Design considerations of GaN devices for improving power converter efficiency 20 Nov 2017
Application note LMK0461x Phase Noise Performance With DC-DC Converters (Rev. B) 20 Jul 2017
Technical article Is it science fiction or 5G? PDF | HTML 19 Sep 2023
White paper Preparing for a 5G world: An overview of the enabling technologies and hardware 17 Dec 2018
Application note Optimizing Layout of the TPS54824 HotRod™ Package for Thermal Performance 16 Nov 2018
Application note JESD204B Multi-Device Synchronization Using LMK0461x 16 Aug 2017
Application note Digital Isolator Design Guide (Rev. G) PDF | HTML 13 Sep 2023
White paper How to measure LDO noise 13 Feb 2017
Analog Design Journal JESD204B multi-device synchronization: Breaking down the requirements 12 May 2015
White paper Analog advancements make waves in 5G communications 12 Aug 2016
Application note TI Network Synchronizer Clock Value Adds in Communications and Industrial Applic 12 Apr 2018
Application note Powering the AFE7920 with the TPS62913 Low-Ripple and Low-Noise Buck Converter (Rev. A) PDF | HTML 11 May 2022
Application note Clocking Optimization for RF Sampling Analog-to-Digital Converters (Rev. A) PDF | HTML 10 May 2022
White paper Advanced Technology and New LDO Features for Highly Demanding Applications 10 Dec 2011
Application note Spurs Analysis in the RF Sampling ADC 09 Feb 2018
Application note RF Sampling ADC with 800MHz of IBW LTE 08 Sep 2016
White paper Internally compensated advanced current mode (ACM) (Rev. A) 07 Dec 2018
White paper Direct RF conversion: From vision to reality 05 May 2015
Application brief Improving RF Power Amplifier Efficiency in 5G Radio Systems 05 Feb 2019

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