This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time mismatch is critical to achieve performance. The complexity of interleaving increases with higher sampling clock. The phase matching between the ADCs is one of the critical specifications to achieve better SFDR and ENOB. This reference design uses the noiseless aperture delay adjustment feature on ADC12DJ5200RF with a 19 fs precise phase control steps that eases 20.8 GSPS interleaving implementation. The reference design uses on-board low noise JESD204B clock generator based on LMK04828 and LMX2594 that meets 12 bit system performance requirement.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Download ready-to-use system files to speed your design process.
Reference design overview and verified performance test data
Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Scalable 20.8 GSPS Reference Design for 12-bit Digitizers | May 22, 2019 | |
| Technical article | Step-by-step considerations for designing wide-bandwidth multichannel systems | PDF | HTML | Jun. 04, 2019 | |
| Design guide | 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide | Mar. 05, 2019 | ||
| White paper | Interleaving ADCs for Higher Sample Rates | Feb. 01, 2005 | ||
| Application note | Defining Skew, Propagation-Delay, Phase Offset (Phase Error) | Nov. 28, 2001 |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.