DS90LV110AT

Name: DS90LV110AT
Brand: TI
SKU: DS90LV110AT
Price: 3.868 USD

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1 bis 10-LVDS-Daten-/Taktverteiler mit Failsafe

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Datenblatt

document-pdfAcrobat DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe datasheet (Rev. J) (Englisch)

DS90LV110AT

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Datenblatt

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Produktdetails

Function

Repeater, Translator

Protocols

CML, LVDS, PECL

Number of transmitters

10

Number of receivers

1

Supply voltage (V)

3.3

Signaling rate (Mbps)

800

Input signal

LVDS, LVPECL, PECL

Output signal

LVDS

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Function

Repeater, Translator

Protocols

CML, LVDS, PECL

Number of transmitters

10

Number of receivers

1

Supply voltage (V)

3.3

Signaling rate (Mbps)

800

Input signal

LVDS, LVPECL, PECL

Output signal

LVDS

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (PW)

28

62.08 mm² 9.7 x 6.4

Low jitter 400 Mbps fully differential data path
145 ps (typ) of pk-pk jitter with PRBS = 2²³−1 data pattern at 400 Mbps
Single +3.3 V Supply
Balanced output impedance
Output channel-to-channel skew is 35ps (typ)
Differential output voltage (V_OD) is 320mV (typ) with 100Ω termination load.
LVDS receiver inputs accept LVPECL signals
LVDS input failsafe
Fast propagation delay of 2.8 ns (typ)
Receiver open, shorted, and terminated input failsafe
28 lead TSSOP package
Conforms to ANSI/TIA/EIA-644 LVDS standard

All trademarks are the property of their respective owners.

Low jitter 400 Mbps fully differential data path
145 ps (typ) of pk-pk jitter with PRBS = 2²³−1 data pattern at 400 Mbps
Single +3.3 V Supply
Balanced output impedance
Output channel-to-channel skew is 35ps (typ)
Differential output voltage (V_OD) is 320mV (typ) with 100Ω termination load.
LVDS receiver inputs accept LVPECL signals
LVDS input failsafe
Fast propagation delay of 2.8 ns (typ)
Receiver open, shorted, and terminated input failsafe
28 lead TSSOP package
Conforms to ANSI/TIA/EIA-644 LVDS standard

All trademarks are the property of their respective owners.

DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz.

The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.

The LVDS outputs can be put into TRI-STATE by use of the enable pin.

For more details, please refer to the APPLICATION INFORMATION section of this datasheet.

DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz.

The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.

The LVDS outputs can be put into TRI-STATE by use of the enable pin.

For more details, please refer to the APPLICATION INFORMATION section of this datasheet.

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Technische Dokumentation

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	Typ	Titel		Datum
*	Data sheet	DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe datasheet (Rev. J)		13 Apr 2013
	Application note	An Overview of LVDS Technology		05 Okt 1998

Design und Entwicklung

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IBIS Model for DS90LV110AT 1 to 10 LVDS Data/Clock Distributor

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DS90LV110AT

1 bis 10-LVDS-Daten-/Taktverteiler mit Failsafe

DS90LV110AT

Produktdetails

Technische Dokumentation

Design und Entwicklung

IBIS Model for DS90LV110AT 1 to 10 LVDS Data/Clock Distributor

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