Startseite Schnittstelle Andere Schnittstellen
Startseite
Schnittstelle
Andere Schnittstellen

DS92LX1621

AKTIV

10 MHz bis 50 MHz, DC-symmetrischer-Channel-Link III-Serializer mit bidirektionalem Steuerkanal

Jetzt bestellen
Datenblatt

DS92LX1621

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RTV) 32 25 mm² 5 x 5
  • Configurable Data Throughput
    • 12–bit (min) up to 600 Mbits/sec
    • 16–bit (def) up to 800 Mbits/sec
    • 18–bit (max) up to 900 Mbits/sec
  • 10 MHz to 50 MHz Input Clock Support
  • Embedded Clock with DC Balanced Coding to
    Support AC-Coupled Interconnects
  • Capable to Drive up to 10 Meters Shielded
    Twisted-Pair
  • Bi-Directional Control Interface Channel with
    I2C Support
  • I2C Interface for Device
    Configuration. Single-pin ID Addressing
  • 16–bit Data Payload with CRC (Cyclic
    Redundancy Check) for Checking Data Integrity
    with Programmable Data Transmission Error
    Detection and Interrupt Control
  • Up to 6 Programmable GPIO’s
  • AT-SPEED BIST Diagnosis Feature to Validate
    Link Integrity
  • Individual Power-Down Controls for Both SER
    and DES
  • User-Selectable Clock Edge for Parallel Data
    on Both SER and DES
  • Integrated Termination Resistors
  • 1.8V- or 3.3V-Compatible Parallel Bus Interface
  • Single Power Supply at 1.8V
  • IEC 61000–4–2 ESD Compliant
  • No Reference Clock Required on Deserializer
  • Programmable Receive Equalization
  • LOCK Output Reporting Pin to Ensure Link
    Status
  • EMI/EMC Mitigation
    • DES Programmable Spread Spectrum (SSCG)
      Outputs
    • DES Receiver Staggered Outputs
  • Temperature Range −40°C to +85°C
  • SER Package: 32 Pin WQFN (5mm × 5mm)
  • DES Package: 40 Pin WQFN (6mm × 6mm)
  • Configurable Data Throughput
    • 12–bit (min) up to 600 Mbits/sec
    • 16–bit (def) up to 800 Mbits/sec
    • 18–bit (max) up to 900 Mbits/sec
  • 10 MHz to 50 MHz Input Clock Support
  • Embedded Clock with DC Balanced Coding to
    Support AC-Coupled Interconnects
  • Capable to Drive up to 10 Meters Shielded
    Twisted-Pair
  • Bi-Directional Control Interface Channel with
    I2C Support
  • I2C Interface for Device
    Configuration. Single-pin ID Addressing
  • 16–bit Data Payload with CRC (Cyclic
    Redundancy Check) for Checking Data Integrity
    with Programmable Data Transmission Error
    Detection and Interrupt Control
  • Up to 6 Programmable GPIO’s
  • AT-SPEED BIST Diagnosis Feature to Validate
    Link Integrity
  • Individual Power-Down Controls for Both SER
    and DES
  • User-Selectable Clock Edge for Parallel Data
    on Both SER and DES
  • Integrated Termination Resistors
  • 1.8V- or 3.3V-Compatible Parallel Bus Interface
  • Single Power Supply at 1.8V
  • IEC 61000–4–2 ESD Compliant
  • No Reference Clock Required on Deserializer
  • Programmable Receive Equalization
  • LOCK Output Reporting Pin to Ensure Link
    Status
  • EMI/EMC Mitigation
    • DES Programmable Spread Spectrum (SSCG)
      Outputs
    • DES Receiver Staggered Outputs
  • Temperature Range −40°C to +85°C
  • SER Package: 32 Pin WQFN (5mm × 5mm)
  • DES Package: 40 Pin WQFN (6mm × 6mm)

The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.

The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package.

The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.

The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package.
filter Andere Andere Schnittstellen suchen
Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 5
Typ Titel Datum
* Data sheet DS92LX1621/1622 10-50MHz DC-Balanced Ch Link III SER/DES w/Bidirectional Ctrl Ch datasheet (Rev. I) 21 Jan 2014
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 29 Apr 2013
User guide LX16EVK01 Channel Link III Ser/Des Evaluation Kit User Guide 25 Jan 2012
Application note Go the Distance: Industrial SerDes with Embedded Clock and Control 20 Okt 2010

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

LX16EVK01 — LX16EVK01-Evaluierungskit

The LX16EVK01 is an evaluation kit designed to demonstrate the performance and capabilities of the DS92LX1621 and DS92LX1622 Channel Link III Serializer/Deserializer chipset.

The DS92LX1621 serializer board accepts LVCMOS input signals for the high speed forward channel and provides additional (...)
Benutzerhandbuch: PDF
Nicht verfügbar auf TI.com
Simulationsmodell

DS92LX1621 IBIS Model

SNLM107.ZIP (115 KB) - IBIS Model
Herunterladen
Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese voll ausgestattete Design- und Simulationssuite verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)
Anfordern
Simulationstool

TINA-TI — SPICE-basiertes analoges Simulationsprogramm

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Benutzerhandbuch: PDF
View Options
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
WQFN (RTV) 32 Ultra Librarian
Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Alle Forenthemen auf Englisch anzeigen

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos