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CD4043B-MIL

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Cierre NOR R/S cuádruple CMOS con salidas de 3 estados

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CD4043B-MIL

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Detalles del producto

Function RS latch Number of channels 4 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type 3-State Data rate (max) (Mbps) 16 IOL (max) (mA) 2.4 IOH (max) (mA) -2.4 Features High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
Function RS latch Number of channels 4 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type 3-State Data rate (max) (Mbps) 16 IOL (max) (mA) 2.4 IOH (max) (mA) -2.4 Features High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • 3-state outputs with common output ENABLE
  • Separate SET and RESET inputs for each latch
  • NOR and NAND configurations
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications
    • Holding register in multi-register system
    • Four bits of independent storage with output ENABLE
    • Strobed register
    • General digital logic
    • CD4043B for positive logic systems
    • CD4044B for negative logic systems

Data sheet acquired from Harris Semiconductor
  • 3-state outputs with common output ENABLE
  • Separate SET and RESET inputs for each latch
  • NOR and NAND configurations
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications
    • Holding register in multi-register system
    • Four bits of independent storage with output ENABLE
    • Strobed register
    • General digital logic
    • CD4043B for positive logic systems
    • CD4044B for negative logic systems

Data sheet acquired from Harris Semiconductor

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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* Data sheet CD4043B, CD4044B Types datasheet (Rev. D) 13 oct 2003

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

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