CD4099B

ACTIVO

Cierre direccionable CMOS de 8 bits

Haga su pedido ahora

Hoja de datos

document-pdfAcrobat CD4099B Types datasheet (Rev. C) (Inglés)

CD4099B

ACTIVO

Hoja de datos

Haga su pedido ahora

Detalles del producto

Function

Addressable Latch

Number of channels

8

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Input type

Standard CMOS

Output type

Push-Pull

Data rate (max) (Mbps)

16

IOL (max) (mA)

2.4

IOH (max) (mA)

-2.4

Features

High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns)

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Function

Addressable Latch

Number of channels

8

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Input type

Standard CMOS

Output type

Push-Pull

Data rate (max) (Mbps)

16

IOL (max) (mA)

2.4

IOH (max) (mA)

-2.4

Features

High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns)

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

Serial data input
Active parallel output
Storage register capability
Master clear
Can function as demultiplexer
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
        1 V at V_DD = 5 V
        2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Multi-line decoders
- A/D converters

Serial data input
Active parallel output
Storage register capability
Master clear
Can function as demultiplexer
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
        1 V at V_DD = 5 V
        2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Multi-line decoders
- A/D converters

CD4099B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.

Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.

A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.

The CD4099B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4099B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.

Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.

A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.

The CD4099B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

filter

Buscar otro/a Otros latches

Descargar