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CD54HC109

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Flip flop J-K con activación lógica de doble borde positivo con CMOS de alta velocidad con Set y Res

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CD54HC109

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Detalles del producto

Number of channels 2 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -6 IOH (max) (mA) 6 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -6 IOH (max) (mA) 6 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Asynchronous Set and Reset
  • Schmitt Trigger Clock Inputs
  • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, A = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH
  • Asynchronous Set and Reset
  • Schmitt Trigger Clock Inputs
  • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, A = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.
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Documentación técnica

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Tipo Título Fecha
* Data sheet CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 datasheet (Rev. E) 13 oct 2003

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

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