CD54HCT175

Name: CD54HCT175
Brand: TI
SKU: CD54HCT175
Price: 17.009 USD

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Flip flops tipo D Quad CMOS Logic de alta velocidad con reset

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Hoja de datos

document-pdfAcrobat CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 datasheet (Rev. C) (Inglés)

CD54HCT175

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Detalles del producto

Number of channels

4

Technology family

HCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

16

IOL (max) (mA)

4

IOH (max) (mA)

-4

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

4

Technology family

HCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

16

IOL (max) (mA)

4

IOH (max) (mA)

-4

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

16

135.3552 mm² 19.56 x 6.92

Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
Positive Edge Pulse Triggering
Complementary Outputs
Buffered Inputs
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
Positive Edge Pulse Triggering
Complementary Outputs
Buffered Inputs
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.

Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.

The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.

Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.

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Documentación técnica

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Ver todo 14

	Tipo	Título		Fecha
*	Data sheet	CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 datasheet (Rev. C)		13 oct 2003
*	SMD	CD54HCT175 SMD 5962-89701		21 jun 2016
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 dic 2022
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 jul 2021
	Selection guide	Logic Guide (Rev. AB)		12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 jul 2004
	User guide	Signal Switch Data Book (Rev. A)		14 nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 ago 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 jun 1997
	Application note	Designing With Logic (Rev. C)		01 jun 1997
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions		01 may 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc		01 abr 1996

Diseño y desarrollo

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
CDIP (J)	16	Ultra Librarian

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CD54HCT175

Flip flops tipo D Quad CMOS Logic de alta velocidad con reset

CD54HCT175

Detalles del producto

Documentación técnica

Diseño y desarrollo

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

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