CD74HC4060

Name: CD74HC4060
Brand: TI
SKU: CD74HC4060
Price: 0.285 USD

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Contador binario con oscilador de 14 etapas Dual CMOS Logic de alta velocidad

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document-pdfAcrobat CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 datasheet (Rev. G) (Inglés)

CD74HC4060

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Detalles del producto

Function

Counter

Bits (#)

14

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Function

Counter

Bits (#)

14

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

TSSOP (PW)

16

32 mm² 5 x 6.4

Onboard Oscillator
Common Reset
Negative Edge Clocking
Fanout (Over Temperature Range)
- Standard Outputs . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor

Onboard Oscillator
Common Reset
Negative Edge Clocking
Fanout (Over Temperature Range)
- Standard Outputs . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor

The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of O). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.

In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.

The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of O). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.

In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.

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Documentación técnica

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Ver todo 14

	Tipo	Título	Fecha
*	Data sheet	CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 datasheet (Rev. G)	16 oct 2003
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	User guide	Signal Switch Data Book (Rev. A)	14 nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 jun 1997
	Application note	Designing With Logic (Rev. C)	01 jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions	01 may 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	01 abr 1996

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que esté en un empaquetado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
PDIP (N)	16	Ultra Librarian
SOIC (D)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

CD74HC4060

Contador binario con oscilador de 14 etapas Dual CMOS Logic de alta velocidad

CD74HC4060

Detalles del producto

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Pin por pin con la misma funcionalidad que el dispositivo comparado

Documentación técnica

Diseño y desarrollo

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

Pedidos y calidad

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