The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function.
The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | 10-Bit Latches With 3-State Outputs datasheet (Rev. A) | 01 oct 2001 |
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