SN54AS74A

ACTIVO

Biestables dobles de tipo D con activación de borde positivo con opciones de eliminación y preajuste

Detalles del producto

Number of channels 2 Technology family AS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 20 IOH (max) (mA) -2 Supply current (max) (µA) 16000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family AS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 20 IOH (max) (mA) -2 Supply current (max) (µA) 16000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm² 19.56 x 6.67
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.

 

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.

 

Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Misma funcionalidad con diferente configuración de pines que el dispositivo comparado
SN74LV2T74-EP ACTIVO Biestables duales de tipo D mejorados con compensación, preajuste y desplazador de nivel integrado Voltage range (1.65V to 5.5V), voltage translation capable

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 13
Tipo Título Fecha
* Data sheet Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. C) 01 ago 1995
* SMD SN54AS74A SMD 5962-98627 21 jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 dic 2022
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note Advanced Schottky Load Management 01 feb 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note Advanced Schottky (ALS and AS) Logic Families 01 ago 1995

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Encapsulado Pines Símbolos CAD, huellas y modelos 3D
CDIP (J) 14 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos