SN54LS109A

ACTIVO

Biestables con activación de borde positivo J-K doble con opciones de preajuste y eliminación

Detalles del producto

Number of channels 2 Technology family LS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL Output type Push-Pull Clock frequency (MHz) 30 Supply current (max) (µA) 15000 IOL (max) (mA) -0.4 IOH (max) (mA) 8 Features Clear, High speed (tpd 10-50ns), Positive edge triggered, Preset Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family LS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL Output type Push-Pull Clock frequency (MHz) 30 Supply current (max) (µA) 15000 IOL (max) (mA) -0.4 IOH (max) (mA) 8 Features Clear, High speed (tpd 10-50ns), Positive edge triggered, Preset Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73
  • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability
  • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C.

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet Dual J-K Positive-Edge-Triggered Flip-Flops With Preset And Clear datasheet 01 mar 1988
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 dic 2022
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 mar 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996

Diseño y desarrollo

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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