Inicio Lógica y traducción de voltaje Biestables, latches y registros Biestables tipo D
Inicio
Lógica y traducción de voltaje
Biestables, latches y registros
Biestables tipo D

SN74ACT74-EP

ACTIVO

Biestables dobles de tipo D con activación de borde positivo con opciones de eliminación y preajuste

Haga su pedido ahora
Hoja de datos

SN74ACT74-EP

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Number of channels 2 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 90 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Number of channels 2 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 90 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
SOIC (D) 14 51.9 mm² 8.65 x 6
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 10.5 ns at 5 V
  • Inputs Are TTL-Voltage Compatible

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 10.5 ns at 5 V
  • Inputs Are TTL-Voltage Compatible

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74ACT74-EP is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE\) or clear (CLR\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

The SN74ACT74-EP is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE\) or clear (CLR\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
filter Buscar otro/a Biestables tipo D
Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Misma funcionalidad con diferente configuración de pines que el dispositivo comparado
SN54SC2T74-SEP ACTIVO Biestables duales de tipo D tolerantes a la radiación con compensación, preajuste y desplazador de n Radiation tolerant version
SN74LV2T74-EP ACTIVO Biestables duales de tipo D mejorados con compensación, preajuste y desplazador de nivel integrado High reliability for enhanced products

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 14
Tipo Título Fecha
* Data sheet SN74ACT74-EP datasheet 30 sep 2003
* VID SN74ACT74-EP VID V6204725 21 jun 2016
* Radiation & reliability report SN74ACT74MDREP Reliability Report 04 jun 2012
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 dic 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 abr 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 14 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos