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SN74ALVCH162721

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Biestable de 20 bits y 3.3 V con salidas de 3 estados

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SN74ALVCH162721

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Detalles del producto

Number of channels 20 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 40 Features Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 20 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 40 Features Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR.

Widebus, EPIC are trademarks of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR.

Widebus, EPIC are trademarks of Texas Instruments.

This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCC operation.

The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored.

A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

The SN74ALVCH162721 is characterized for operation from –40°C to 85°C.

This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCC operation.

The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored.

A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

The SN74ALVCH162721 is characterized for operation from –40°C to 85°C.
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Documentación técnica

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* Data sheet SN74ALVCH162721 datasheet (Rev. G) 17 sep 2004
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 dic 2022
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 17 sep 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 01 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 sep 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 03 ago 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 13 may 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

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Modelo de simulación

SN74ALVCH162721 IBIS Model (Rev. B)

SCEM025B.ZIP (71 KB) - IBIS Model
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SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
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Pedidos y calidad

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