SN74AUC240

Name: SN74AUC240
Brand: TI
SKU: SN74AUC240
Price: 0.402 USD

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Inversores de alta velocidad, de 8 canales, 0.8 V a 2.7 V con salidas de 3 estados

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Hoja de datos

document-pdfAcrobat SN74AUC240 datasheet (Rev. A) (Inglés)

SN74AUC240

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Detalles del producto

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

8

IOL (max) (mA)

9

IOH (max) (mA)

-9

Supply current (max) (µA)

20

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

8

IOL (max) (mA)

9

IOH (max) (mA)

-9

Supply current (max) (µA)

20

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

VQFN (RGY)

20

15.75 mm² 4.5 x 3.5

Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub 1-V Operable
Max t_pd of 1.7 ns at 1.8 V
Low Power Consumption, 20-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub 1-V Operable
Max t_pd of 1.7 ns at 1.8 V
Low Power Consumption, 20-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This octal buffer/driver is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

This device is organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This octal buffer/driver is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

This device is organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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SN74LVC240A

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Inversores de 8 canales, 1.65 V a 3.6 V con salidas de 3 estados Higher average drive strength (24mA), longer average propagation delay (5.5ns)

Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	SN74AUC240 datasheet (Rev. A)	20 mar 2003
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	04 nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 jun 2004
	User guide	Signal Switch Data Book (Rev. A)	14 nov 2003
	Application note	Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices	21 mar 2003
	User guide	AUC Data Book, January 2003 (Rev. A)	01 ene 2003
	Application note	Texas Instruments Little Logic Application Report	01 nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 jun 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	27 mar 2002
	More literature	AUC Product Brochure (Rev. A)	18 mar 2002

Diseño y desarrollo

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Placa de evaluación

14-24-NL-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados sin conductores de 14 a 24 pine

14-24-NL-LOGIC-EVM es un módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo lógico o de traducción que tenga un encapsulado BQA, BQB, RGY, RSV, RJW o RHL de 14 a 24 pines.

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