SN74LS194A

ACTIVO

Registros de desplazamiento universal bidireccional

alarmNotificaciones Haga su pedido ahora

Detalles del producto

Configuration Universal Bits (#) 4 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 63000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Universal Bits (#) 4 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 63000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6
  • Parallel Inputs and Outputs
  • Four Operating Modes:
    • Synchronous Parallel Load
    • Right Shift
    • Left Shift
    • Do Nothing
  • Positive Edge-Triggered Clocking
  • Direct Overriding Clear

 

  • Parallel Inputs and Outputs
  • Four Operating Modes:
    • Synchronous Parallel Load
    • Right Shift
    • Left Shift
    • Do Nothing
  • Positive Edge-Triggered Clocking
  • Direct Overriding Clear

 

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

  • Inhibit clock (do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.

Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high.

 

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

  • Inhibit clock (do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.

Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high.

 

Descargar

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Funcionalidad similar a la del dispositivo comparado
SN74HC595 ACTIVO Registros de desplazamiento de 8 bits con registros de salida de 3 estados Voltage range (2V to 6V), average drive strength (8mA), average propagation delay (20ns)

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 1
Tipo Título Fecha
* Data sheet 4-Bit Bidirectional Universal Shift Registers datasheet 01 mar 1988

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​