Inicio Lógica y traducción de voltaje Búferes, controladores y transceptores Transceptores de uso general
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Lógica y traducción de voltaje
Búferes, controladores y transceptores
Transceptores de uso general

SN74LVCR16245A

ACTIVO

TRANSCEPTOR DE BUS DE 16 BITS CON SALIDAS DE 3 ESTADOS

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SN74LVCR16245A

ACTIVO
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Detalles del producto

Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type TTL/CMOS Output type LVTTL Features Balanced outputs Technology family LVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type TTL/CMOS Output type LVTTL Features Balanced outputs Technology family LVC Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Member of the Texas Instruments
    Widebus Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°D
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on
    All Ports (5-V Input/Output Voltage With
    3.3-V VCC)
  • All Inputs and Outputs Have Equivalent 26-Ω
    Series Resistors, So No External Resistors
    Are Required
  • Ioff Supports Live Insertion,
    Partial-Power-Down Mode, and Back-Drive
    Protection
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Member of the Texas Instruments
    Widebus Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°D
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on
    All Ports (5-V Input/Output Voltage With
    3.3-V VCC)
  • All Inputs and Outputs Have Equivalent 26-Ω
    Series Resistors, So No External Resistors
    Are Required
  • Ioff Supports Live Insertion,
    Partial-Power-Down Mode, and Back-Drive
    Protection
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCR16245A device is designed for asynchronous communication between data buses. All inputs and outputs have equivalent 26-Ω resistors that will slow the edges of the output and reduce switching noise caused by long capacitive etch runs or cables.

This device can be used as two 8-bit transceivers or one 16-bit transceiver. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state.

For all available packages, see the orderable addendum at the end of the datasheet.

This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCR16245A device is designed for asynchronous communication between data buses. All inputs and outputs have equivalent 26-Ω resistors that will slow the edges of the output and reduce switching noise caused by long capacitive etch runs or cables.

This device can be used as two 8-bit transceivers or one 16-bit transceiver. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state.

For all available packages, see the orderable addendum at the end of the datasheet.
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Documentación técnica

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* Data sheet SN74LVCR16245A 16-Bit Bus Transceiver with 3-State Outputs datasheet (Rev. B) PDF | HTML 06 may 2014
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN74LVCR16245A IBIS Model (Rev. A)

SCAM039A.ZIP (41 KB) - IBIS Model
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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