SN74LVTH273

Name: SN74LVTH273
Brand: TI
SKU: SN74LVTH273
Price: 0.263 USD

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Biestables de tipo D octales ABT de 3.3 V con opción de eliminación

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document-pdfAcrobat SN54LVTH273, SN74LVTH273 datasheet (Rev. M) (Inglés)

SN74LVTH273

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Detalles del producto

Number of channels

8

Technology family

LVT

Supply voltage (min) (V)

2.7

Supply voltage (max) (V)

3.6

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Features

Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

LVT

Supply voltage (min) (V)

2.7

Supply voltage (max) (V)

3.6

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Features

Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

SSOP (DB)

20

56.16 mm² 7.2 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Support Unregulated Battery Operation Down to 2.7 V
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
I_off Supports Partial-Power-Down-Mode Operation
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Support Unregulated Battery Operation Down to 2.7 V
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
I_off Supports Partial-Power-Down-Mode Operation
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	SN54LVTH273, SN74LVTH273 datasheet (Rev. M)		13 oct 2003
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 dic 2022
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 jul 2021
	Application note	An Overview of Bus-Hold Circuit and the Applications (Rev. B)		17 sep 2018
	Selection guide	Logic Guide (Rev. AB)		12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 ago 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		22 may 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		10 may 2002
	Selection guide	Advanced Bus Interface Logic Selection Guide		09 ene 2001
	Application note	LVT-to-LVTH Conversion		08 dic 1998
	Application note	LVT Family Characteristics (Rev. A)		01 mar 1998
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 ago 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 oct 1996
	Application note	Live Insertion		01 oct 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide		01 may 1996

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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