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DP83865

新規設計での使用を推奨しません

ギガビット対応、10/100/1000、PHYTER V イーサネット物理層トランシーバ

ご注文はこちら
データシート
DP83865 は新規設計での使用を推奨しません
これまでにご購入されたお客様をサポートする目的でこの製品を引き続き生産しています。新規設計では代替品をご検討ください。
open-in-new 代替品と比較
比較対象デバイスと類似の機能
DP83867E アクティブ 拡張温度範囲、SGMII 対応、高い信頼性、低レイテンシ、ギガビット・イーサネット PHY トランシーバ The DP83867E requires less than half the power of the DP83865 and has higher temperature range.

DP83865

新規設計での使用を推奨しません
データシート ご注文はこちら

製品詳細

Datarate (Mbps) 10/100/1000 Interface type GMII, MII, RGMII Number of ports Single Rating Catalog Supply voltage (V) 1.8 Operating temperature range (°C) 0 to 70 Number of LEDs 5 ESD HBM (kV) 6
Datarate (Mbps) 10/100/1000 Interface type GMII, MII, RGMII Number of ports Single Rating Catalog Supply voltage (V) 1.8 Operating temperature range (°C) 0 to 70 Number of LEDs 5 ESD HBM (kV) 6
QFP (NND) 128 399.04 mm² 23.2 x 17.2
  • Ultra low power consumption typically 1.1 watt
  • Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
  • Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
  • 3.3V or 2.5V MAC interfaces:
  • IEEE 802.3u MII
  • IEEE 802.3z GMII
  • RGMII version 1.3
  • User programmable GMII pin ordering
  • IEEE 802.3u Auto-Negotiation and Parallel Detection
  • Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
  • Speed Fallback mode to achieve quality link
  • Cable length estimator
  • LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
  • Supports 25 MHz operation with crystal or oscillator.
  • Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
  • User programable interrupt
  • Supports Auto-MDIX at 10, 100 and 1000 Mb/s
  • Supports JTAG (IEEE1149.1)
  • 128-pin PQFP package (14mm x 20mm)
  • Ultra low power consumption typically 1.1 watt
  • Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
  • Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
  • 3.3V or 2.5V MAC interfaces:
  • IEEE 802.3u MII
  • IEEE 802.3z GMII
  • RGMII version 1.3
  • User programmable GMII pin ordering
  • IEEE 802.3u Auto-Negotiation and Parallel Detection
  • Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
  • Speed Fallback mode to achieve quality link
  • Cable length estimator
  • LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
  • Supports 25 MHz operation with crystal or oscillator.
  • Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
  • User programable interrupt
  • Supports Auto-MDIX at 10, 100 and 1000 Mb/s
  • Supports JTAG (IEEE1149.1)
  • 128-pin PQFP package (14mm x 20mm)

The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility.

The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).

The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.

The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility.

The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).

The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer データシート (Rev. B) 2007年 12月 11日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点