パッケージ情報
| パッケージ | ピン数 TSSOP (DGG) | 48 |
| 動作温度範囲 (℃) -10 to 70 |
| パッケージ数量 | キャリア 38 | TUBE |
DS90CR218A の特徴
- 12 to 85 MHz shift clock support
- 50% duty cycle on receiver output clock
- Low power consumption
- ±1V common-mode range (around +1.2V)
- Narrow bus reduces cable size and cost
- Up to 1.785 Gbps throughput
- Up to 223 Mbytes/sec bandwidth
- 345 mV (typ) swing LVDS devices for low EMI
- PLL requires no external components
- Rising edge data strobe
- Compatible with TIA/EIA-644 LVDS standard
- Low profile 48-lead TSSOP package
DS90CR218A に関する概要
The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. When operating at the maximum input clock rate of 85 Mhz, the LVDS data is received at 595 Mbps per data channel for a total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.