CLC001
- Adjustable output amplitude
- Differential input and output
- Accepts LVPECL or LVDS input swings
- Low power dissipation
- Single +3.3V supply
The CLC001 is a monolithic, high-speed cable driver designed for use in SMPTE 259M serial digital video and ITU-T G.703 serial digital data transmission applications. The CLC001 drives 75
transmission lines (Belden 8281 or equivalent) at data rates up to 622 Mbps. Controlled output rise and fall times (400 ps typical) minimize transition-induced jitter. The output voltage swing is adjustable from 800 mVp-p to 1.0 Vp-p using an external resistor.
The CLC001's output stage consumes less power than other designs. The differential inputs accept LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.
All these make the CLC001 an excellent general purpose high speed driver for high-speed, long distance data transmission applications.
The CLC001 is powered from a single +3.3V supply and comes in a small 8-pin SOIC package.
Key Specifications
- 400 ps rise and fall times
- Data rates to 622 Mbps
- 100 mV differential input threshold
- Low residual jitter
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | CLC001 Serial Digital Cable Driver with Adjustable Outputs datasheet (Rev. B) | 2006/02/15 | |
| Application note | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 2013/04/26 | ||
| Application note | AN-2059 Replacing the CLC001 Cable Driver with the LMH0001 (Rev. B) | 2013/04/26 | ||
| Application note | AN-2145 Power Considerations for SDI Products (Rev. B) | 2013/04/26 | ||
| Application note | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 2013/04/26 | ||
| Application note | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 2009/11/12 | ||
| White paper | Hundreds of Megabits @ Hundreds of Meters: Extend the Transmis Length for LVDS | 2004/09/01 | ||
| Application note | 3.3V Cable Driver And Equalizer Drive Mega-Bits @ Many Meters | 2003/03/06 | ||
| White paper | Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches | 2001/08/01 |
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치