DS32EL0421
- 5-bit DDR LVDS Parallel Data Interface
- Programmable Transmit De-emphasis
- Configurable Output Levels (VOD)
- Selectable DC-balanced Encoder
- Selectable Data Scrambler
- Remote Sense for Automatic Detection and Negotiation of Link Status
- On Chip LC VCOs
- Redundant Serial Output (ELX device only)
- Data Valid Signaling to Assist with Synchronization of Multiple Receivers
- Supports AC- and DC-coupled Signaling
- Integrated CML and LVDS Terminations
- Configurable PLL Loop Bandwidth
- Programmable Output Termination (50Ω or 75Ω).
- Built-in Test Pattern Generator
- Loss of Lock and Error Reporting
- Configurable via SMBus
- 48-pin WQFN Package with Exposed DAP
Key Specifications
- 1.25 to 3.125 Gbps Serial Data Rate
- 125 to 312.5 MHz DDR Parallel Clock
- -40° to +85°C Temperature Range
- >8 kV ESD (HBM) Protection
- Low Intrinsic Jitter — 35ps at 3.125 Gbps
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The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS32EL0421/ELX0421 125 - 312.5 MHz FPGA-Link Serializer w/ DDR LVDS Parallel I/F datasheet (Rev. F) | 2013/04/15 | |
| Application note | Expanding the Payload w/FPGA-Link DS32ELX0421 and DS32ELX0124 SER/DES (Rev. A) | 2013/04/26 | ||
| Application note | LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers (Rev. A) | 2013/04/26 |
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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