DS92CK16
- Master/Slave Clock Selection in a Backplane Application
- 125 MHz Operation (Typical)
- 100 ps Duty Cycle Distortion (Typical)
- 50 ps Channel to Channel Skew (Typical)
- 3.3V Power Supply Design
- Glitch-free Power on at CLKI/O Pins
- Low Power Design (20 mA @ 3.3V Static)
- Accepts Small Swing (300 mV Typical) Differential Signal Levels
- Industrial Temperature Operating Range (-40°C to +85°C)
- Available in 24-pin TSSOP Packaging
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The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high data rates. The BLVDS side is a transceiver with a separate channel acting as a return/source clock.
The DS92CK16 accepts LVDS (300 mV typical) differential input levels, and translates them to 3V CMOS output levels. An output enable pin OE , when high, forces all CLKOUT pins high.
The device can be used as a source synchronous driver. The selection of the source driving is controlled by the CrdCLKIN and DE pins. This device can be the master clock, driving the inputs of other clock I/O pins in a multipoint environment. Easy master/slave clock selection is achieved along a backplane.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver datasheet (Rev. C) | 2013/04/13 | |
| Application note | High Speed BUS LVDS Clock Distri Using DS92CK16 Clock Distri (Rev. B) | 2013/04/26 |
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (PW) | 24 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치