인터페이스 기타 인터페이스

DS92LV0422

활성

LVDS 병렬 인터페이스를 지원하는 10~75MHz 채널 링크 II 디시리얼라이저

제품 상세 정보

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RHS) 48 49 mm² 7 x 7
  • 5-Channel (4 Data + 1 Clock) Channel Link LVDS Parallel Interface Supports 24-Bit Data 3-Bit Control at 10 to 75 MHz
  • AC-Coupled STP Interconnect Up to 10 m
  • Integrated Terminations on Serializer and Deserializer
  • At-Speed Link BIST Mode and Reporting Pin
  • Optional I2C-Compatible Serial Control Bus
  • Power-Down Mode Minimizes Power Dissipation
  • 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
  • >8-kV HBM
  • –40° to 85°C Temperature Range
  • Serializer (DS92LV0421)
    • Data Scrambler for Reduced EMI
    • DC-Balance Encoder for AC Coupling
    • Selectable Output VOD and Adjustable De-Emphasis
  • Deserializer (DS92LV0422)
    • Fast Random Data Lock; No Reference Clock Required
    • Adjustable Input Receiver Equalization
    • EMI Minimization on Output Parallel Bus (SSCG and LVDS VOD Select)
  • 5-Channel (4 Data + 1 Clock) Channel Link LVDS Parallel Interface Supports 24-Bit Data 3-Bit Control at 10 to 75 MHz
  • AC-Coupled STP Interconnect Up to 10 m
  • Integrated Terminations on Serializer and Deserializer
  • At-Speed Link BIST Mode and Reporting Pin
  • Optional I2C-Compatible Serial Control Bus
  • Power-Down Mode Minimizes Power Dissipation
  • 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
  • >8-kV HBM
  • –40° to 85°C Temperature Range
  • Serializer (DS92LV0421)
    • Data Scrambler for Reduced EMI
    • DC-Balance Encoder for AC Coupling
    • Selectable Output VOD and Adjustable De-Emphasis
  • Deserializer (DS92LV0422)
    • Fast Random Data Lock; No Reference Clock Required
    • Adjustable Input Receiver Equalization
    • EMI Minimization on Output Parallel Bus (SSCG and LVDS VOD Select)

The DS92LV042x chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV042x enables applications currently using popular Channel Link or OpenLDI LVDS style devices to upgrade seamlessly to an embedded clock interface. This serial bus scheme reduces interconnect cost and eases design challenges. The parallel OpenLDI LVDS interface also reduces FPGA I/O pins, board trace count, and alleviates EMI issues when compared to traditional single-ended wide bus interfaces.

Programmable transmit de-emphasis, receive equalization, on-chip scrambling, and DC-balancing enables longer distance transmission over lossy cables and backplanes. The DS92LV0422 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy operation.

The DS92LV042x chipset is programmable through an I2C interface as well as through pins. A built-in, at-speed BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0421 and DS92LV0422 can be used interchangeably with the DS92LV2421 or DS92LV2422. This allows designers the flexibility to connect to the host device and receiving devices with different interface types: LVDS or LVCMOS.

The DS92LV042x chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV042x enables applications currently using popular Channel Link or OpenLDI LVDS style devices to upgrade seamlessly to an embedded clock interface. This serial bus scheme reduces interconnect cost and eases design challenges. The parallel OpenLDI LVDS interface also reduces FPGA I/O pins, board trace count, and alleviates EMI issues when compared to traditional single-ended wide bus interfaces.

Programmable transmit de-emphasis, receive equalization, on-chip scrambling, and DC-balancing enables longer distance transmission over lossy cables and backplanes. The DS92LV0422 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy operation.

The DS92LV042x chipset is programmable through an I2C interface as well as through pins. A built-in, at-speed BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0421 and DS92LV0422 can be used interchangeably with the DS92LV2421 or DS92LV2422. This allows designers the flexibility to connect to the host device and receiving devices with different interface types: LVDS or LVCMOS.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
6개 모두 보기
유형 직함 날짜
* Data sheet DS92LV042x 10-MHz to-75 MHz Channel Link II Serializer and Deserializer With LVDS Parallel Interface datasheet (Rev. D) PDF | HTML 2016/12/16
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018/11/09
Technical article Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind PDF | HTML 2017/08/24
Application note DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 2013/04/29
User guide LV04EVK01 Channel Link to Channel Link II Converter Evaluation Kit 2012/02/01
Design guide Channel Link II Design Guide 2011/01/21

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

DS92LV0422 IBIS Model

SNLM131.ZIP (172 KB) - IBIS Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
WQFN (RHS) 48 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상