DS92LV090A
- Bus LVDS Signaling
- 3.2 Nanosecond Propagation Delay Max
- Chip to Chip Skew ±800ps
- Low Power CMOS Design
- High Signaling Rate Capability (Above 100 Mbps)
- 0.1V to 2.3V Common Mode Range for VID = 200mV
- ±100 mV Receiver Sensitivity
- Supports Open and Terminated Failsafe on Port Pins
- 3.3V Operation
- Glitch Free Power Up/Down (Driver & Receiver Disabled)
- Light Bus Loading (5 pF Typical) per Bus LVDS Load
- Designed for Double Termination Applications
- Balanced Output Impedance
- Product Offered in 64 Pin LQFP Package
- High Impedance Bus Pins on Power off (VCC = 0V)
- Driver Channel to Channel Skew (Same Device) 230ps Typical
- Receiver Channel to Channel Skew (Same Device) 370ps Typical
All trademarks are the property of their respective owners.
The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.
The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Section for more details.)
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS92LV090A 9 Channel Bus LVDS Transceiver datasheet (Rev. D) | 2013/05/19 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| LQFP (PM) | 64 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.