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DS92LV3242

마지막 구매

20~85MHz 32비트 채널 링크 II 디시리얼라이저

지금 주문
데이터 시트

DS92LV3242

마지막 구매
데이터 시트 지금 주문

제품 상세 정보

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
TQFP (PAG) 64 144 mm² 12 x 12
  • Wide Operating Range Embedded Clock SER/DES
    • Up to 32-bit Parallel LVCMOS Data
    • 20 to 85 MHz Parallel Clock
    • Up to 2.72 Gbps Application Data Paylod
  • Selectable Serial LVDS Bus Width
    • Dual Lane Mode (20 to 50 MHz)
    • Quad Lane Mode (40 to 85 MHz)
  • Simplified Clocking Architecture
    • No Separate Serial Clock Line
    • No reference Clock Required
    • Receiver Locks to Random Data
  • On-Chip Signal Conditioning for Robust Serial Connectivity
    • Transmit Pre-Emphasis
    • Data Randomization
    • DC-Balance Encoding
    • Receive Channel Deskew
    • Supports up to 10m CAT-5 at 2.7 Gbps
  • Integrated LVDS Terminations
  • Built-in AT-SPEED BIST for End-to-End System Testing
  • AC-Coupled Interconnect for Isolation and Fault Protection
  • > 4KV HBM ESD Protection
  • Space-Saving 64-pin TQFP Package
  • Full Industrial Temperature Range : -40° to +85°C

All trademarks are the property of their respective owners.

  • Wide Operating Range Embedded Clock SER/DES
    • Up to 32-bit Parallel LVCMOS Data
    • 20 to 85 MHz Parallel Clock
    • Up to 2.72 Gbps Application Data Paylod
  • Selectable Serial LVDS Bus Width
    • Dual Lane Mode (20 to 50 MHz)
    • Quad Lane Mode (40 to 85 MHz)
  • Simplified Clocking Architecture
    • No Separate Serial Clock Line
    • No reference Clock Required
    • Receiver Locks to Random Data
  • On-Chip Signal Conditioning for Robust Serial Connectivity
    • Transmit Pre-Emphasis
    • Data Randomization
    • DC-Balance Encoding
    • Receive Channel Deskew
    • Supports up to 10m CAT-5 at 2.7 Gbps
  • Integrated LVDS Terminations
  • Built-in AT-SPEED BIST for End-to-End System Testing
  • AC-Coupled Interconnect for Isolation and Fault Protection
  • > 4KV HBM ESD Protection
  • Space-Saving 64-pin TQFP Package
  • Full Industrial Temperature Range : -40° to +85°C

All trademarks are the property of their respective owners.

The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.

On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation.

By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.

On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation.

By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.
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* Data sheet DS92LV3241/3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer datasheet (Rev. D) 2013/04/16

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치