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DS99R104

마지막 구매

3~40MHz DC 균형 24비트 LVDS 디시리얼라이저(-40C~85C 온도 지원)

지금 주문
데이터 시트

DS99R104

마지막 구매
데이터 시트 지금 주문

제품 상세 정보

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
TQFP (PFB) 48 81 mm² 9 x 9 WQFN (NJU) 48 49 mm² 7 x 7
  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS inputs and control pins have internal pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range −40°C to +85°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS inputs and control pins have internal pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range −40°C to +85°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
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* Data sheet DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet (Rev. D) 2013/04/16

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치