LM2502
- >300 Mbps Dual Link Raw Throughput
- MPL Physical Layer (MPL-0)
- Pin Selectable Master / Slave Mode
- Frequency Reference Transport
- Complete LVCMOS / MPL Translation
- Interface Modes:
- 16-bit CPU, i80 or m68 Style
- RGB565 with Glue Logic
- −30°C to 85°C Operating Range
- Link Power Down Mode Reduces IDDZ < 10 µA
- Dual Display Support (CS1* & CS2*)
- Via-less MPL Interconnect Feature
- 3.0V Supply Voltage (VDD and VDDA)
- Interfaces to 1.7V to 3.3V Logic (VDDIO)
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The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. The chipset may also be used for a RGB565 application with glue logic. The interconnect is reduced from 22 signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost.
The Master Serializer (SER) resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Deserializer (DES) located near the display module.
Dual display support is provided for a primary and sub display through the use of two ChipSelect signals. A Mode pin selects either a i80 or m68 style interface.
The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD1/0 and MC signals are powered down to save current.
The LM2502 implements the physical layer of the MPL Standard (MPL-0). The LM2502 is offered in NOPB (Lead-free) NFBGA and WQFN packages.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer datasheet (Rev. L) | 2013/05/02 | |
| Application note | Mobile Pixel Link Level-0 | 2012/03/20 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WQFN (RSB) | 40 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치