LM5025B
- Internal Start-Up Bias Regulator
- 3A Compound Main Gate Driver
- Programmable Line Under-Voltage Lockout (UVLO) with Adjustable Hysteresis
- Voltage Mode Control with Feed-Forward
- Adjustable Dual Mode Over-Current Protection
- Programmable Overlap or Deadtime between the Main and Active Clamp Outputs
- Volt x Second Maximum Duty Cycle Clamp
- Programmable Soft-Start
- Current Sense Leading Edge Blanking
- Single Resistor Programmable Oscillator
- Oscillator Up / Down Sync Capability
- Precision 5V Reference
- Thermal Shutdown
Packages
- TSSOP-16
- WSON-16 (5x5 mm) Thermally Enhanced
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The LM5025B is a functional variant of the LM5025 active clamp PWM controller. The functional differences of the LM5025B are as follows:
- The maximum PWM duty cycle is limited to less than 75% to reduce voltage stress on the power MOSFETs.
- The CS2 hiccup mode threshold is increased to 0.5V
- The CS2 filter discharge device is disabled
- The VCC regulator continues to operate when the line UVLO is below the threshold of normal operation
- The VREF regulator is switched off when the line UVLO input falls below the operating threshold
- The internal 5kΩ COMP pin pull-up resistor is removed
The LM5025B PWM controller contains all of the features necessary to implement power converters utilizing the Active Clamp / Reset technique. With the active clamp technique, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The two internal compound gate drivers parallel both MOS and Bipolar devices, providing superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less than 100ns.
The LM5025B includes a high-voltage start-up regulator that operates over a wide input range of 13V to 100V. Additional features include: Line Under Voltage Lockout (UVLO), softstart, oscillator UP/DOWN sync capability, precision reference and thermal shutdown.
기술 자료
설계 및 개발
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LM5025B Unencrypted PSpice Transient Model Package (Rev. A)
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
TSSOP (PW) | 16 | Ultra Librarian |
WSON (NHQ) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치