LM5115
- Self-Synchronization to Main Channel Output
- Standalone DC/DC Synchronous Buck Mode
- Leading Edge Pulse Width Modulation
- Voltage-Mode Control with Current Injection and Input Line Feed-Forward
- Operates from AC or DC Input up to 75V
- Wide 4.5V to 30V Bias Supply Range
- Wide 0.75V to 13.5V Output Range.
- Top and Bottom Gate Drivers Sink 2.5A Peak
- Adaptive Gate Driver Dead-Time Control
- Wide Bandwidth Error Amplifier (4MHz)
- Programmable Soft-Start
- Thermal Shutdown Protection
- TSSOP-16 or Thermally Enhanced WSON-16 Packages
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The LM5115 is a versatile switching regulator controller. It has two main application configurations. The first is utilizing the Secondary Side Post Regulation (SSPR) technique to implement multiple output power converters. In the second configuration, it can be used as a standalone synchronous buck controller (Please see for more details). The SSPR technique develops a highly efficient and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter. Regulation of the auxiliary output voltage is achieved by leading edge pulse width modulation (PWM) of the main channel duty cycle. Leading edge modulation is compatible with either current mode or voltage mode control of the main output. The LM5115 drives external high side and low side NMOS power switches configured as a synchronous buck regulator. A current sense amplifier provides overload protection and operates over a wide common mode input range. Additional features include a low dropout (LDO) bias regulator, error amplifier, precision reference, adaptive dead time control of the gate signals and thermal shutdown.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | LM5115 Secondary Side Post Regulator / Synchronous Buck Controller datasheet (Rev. E) | 2013/03/21 | |
| White paper | Valuing wide VIN, low EMI synchronous buck circuits for cost-driven, demanding a (Rev. A) | 2019/04/10 | ||
| Analog Design Journal | Reduce buck-converter EMI and voltage stress by minimizing inductive parasitics | 2016/07/21 | ||
| EVM User's guide | AN-1368 LM5115/5025A Evaluation Board (Rev. A) | 2013/04/26 | ||
| EVM User's guide | AN-1367 LM5115 HV DC Evaluation Board (Rev. B) | 2013/04/24 | ||
| EVM User's guide | AN-1542 LM5115A Evaluation Board (Rev. B) | 2013/04/24 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
| WSON (NHQ) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치