SN65CML100
- Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML
- Signaling Rates1 up to 1.5 Gbps
- CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
- Total Jitter < 70 ps
- Low 100 ps (Max) Part-To-Part Skew
- Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals
- 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
- Propagation Delay Times, 800 ps Maximum
- 3.3-V Supply Operation
- Available in SOIC and MSOP Packages
- APPLICATIONS
- Level Translation
- 622-MHz Central Office Clock Distribution
- High-Speed Network Routing
- Wireless Basestations
- Low Jitter Clock Repeater
1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50-
loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.
The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBB should be left open.
This device is characterized for operation from –40°C to 85°C.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | 1.5-Gbps LVDS/LVPECL/CML-to-CML Translator/Repeater datasheet | 2002/11/11 | |
| Application note | Signaling Rate vs. Distance for Differential Buffers | 2010/01/26 | ||
| EVM User's guide | 2-GBPS Differential Repeater EVM (Rev. A) | 2002/11/11 |
설계 및 개발
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SN65CML100EVM — SN65CML100 평가 모듈
The EVM allows evaluation of operation of theSN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters. Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can beobserved across on board terminations, or via direct connection to 50-ohm (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.