SN65DSI85
- Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
- Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
- Supports 18-bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
- Suitable for 60 fps WQXGA 2560 × 1600 resolution at 18-bpp and 24-bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
- MIPI® front-end configurable for single-channel or dual-channel DSI configurations
- FlatLink™ output configurable for single-link or dual-link LVDS
- Supports dual-channel DSI ODD or EVEN and LEFT or RIGHT operating modes
- Supports two single-channel DSI to two single-link LVDS operating mode
- LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link mode
- LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
- 1.8-V main VCC power supply
- Low-power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI® ultra-low power state (ULPS) support
- LVDS channel swap, LVDS pin order reverse feature for ease of PCB routing
- ESD rating ±2 kV (HBM)
- Packaged in 64-pin 5 mm x 5 mm nFBGA (ZXH)
- Temperature range: –40°C to 85°C
The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.
The SN65DSI85 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
Designed with industry-compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.
The SN65DSI85 is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.
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기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN65DSI85 MIPI® DSI Bridge to FlatLink LVDS Dual Channel DSI to Dual-Link LVDS datasheet (Rev. G) | 2020/10/01 | |
| Application note | Troubleshooting SN65DSI8x - Tips and Tricks | 2018/08/27 | ||
| EVM User's guide | SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide | 2015/11/17 | ||
| Application note | SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A) | 2013/04/11 | ||
| Application note | SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B) | 2013/04/08 |
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PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| NFBGA (ZXH) | 64 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
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