SN65LVDS047
- >400 Mbps (200 MHz) Signaling Rates
- Flow-Through Pinout Simplifies PCB Layout
- 300 ps Maximum Differential Skew
- Propagation Delay Times 1.8 ns (Typical)
- 3.3 V Power Supply Design
- ±350 mV Differential Signaling
- High Impedance on LVDS Outputs on Power Down
- Conforms to TIA/EIA-644 LVDS Standard
- Industrial Operating Temperature Range (–40°C to 85°C)
- Available in SOIC and TSSOP Packages
The SN65LVDS047 is a quad differential line driver that implements the electrical characteristics
of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode
drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-
load
when enabled.
The intended application of this device and signaling technique is for point-to-point and multi-drop
baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces,
backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS047 is characterized for operation from -40°C to 85°C.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | LVDS Quad Differential Line Driver datasheet (Rev. B) | 2003/12/01 | |
| Application note | Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B) | PDF | HTML | 2021/09/07 | |
| Application brief | LVDS to Improve EMC in Motor Drives | 2018/09/27 | ||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018/08/03 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018/05/16 | ||
| Technical article | Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind | PDF | HTML | 2017/08/24 | |
| Application note | An Overview of LVDS Technology | 1998/10/05 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.