SN65LVDS1
- Meets or Exceeds the ANSI TIA/EIA-644 Standard
- Designed for Signaling Rates (1) up to:
- 630Mbps for Drivers
- 400Mbps for Receivers
- Operates From a 2.4V to 3.6V Supply
- Available in SOT-23 and SOIC Packages
- Bus-Terminal ESD Exceeds 9kV
- Low-Voltage Differential Signaling With Typical Output Voltages of 350mV Into a 100Ω Load
- Propagation Delay Times
- 1.7ns Typical Driver
- 2.5ns Typical Receiver
- Power Dissipation at 200MHz
- 25mW Typical Driver
- 60mW Typical Receiver
- LVDT Receiver Includes Line Termination
- Low Voltage TTL (LVTTL) Level Driver Input Is 5V Tolerant
- Driver Is Output High-Impedance with VCC < 1.5V
- Receiver Output and Inputs are High-Impedance With VCC < 1.5V
- Receiver Open-Circuit Fail Safe
- Differential Input Voltage Threshold Less Than 100mV
(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second)
The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are single, low-voltage, differential line drivers and receivers in the small-outline transistor package. The outputs comply with the TIA/EIA-644 standard and provide a minimum differential output voltage magnitude of 247mV into a 100Ω load at signaling rates up to 630Mbps for drivers and 400Mbps for receivers.
When the SN65LVDS1 device is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make the device ideal for battery-powered applications.
The SN65LVDS1, SN65LVDS2, and SN65LVDT2 devices are characterized for operation from –40°C to 85°C.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN65LVDxx High-Speed Differential Line Drivers and Receivers datasheet (Rev. M) | PDF | HTML | 2024/03/01 |
| Application brief | How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver | 2019/01/09 | ||
| Application brief | How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter | 2018/12/28 | ||
| Application brief | LVDS to Improve EMC in Motor Drives | 2018/09/27 | ||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018/08/03 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018/05/16 | ||
| Application note | An Overview of LVDS Technology | 1998/10/05 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| SOT-23 (DBV) | 5 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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