SN65LVDS101
- Designed for Signaling Rates ≥ 2 Gbps
- Total Jitter < 65 ps
- Low-Power Alternative for the MC100EP16
- Low 100-ps (Maximum) Part-to-Part Skew
- 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Input Voltage Range - Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels - 3.3-V Supply Operation
- LVDT Integrates 110-Ω Terminating Resistor
- Offered in SOIC and MSOP
The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.
The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.
All devices are characterized for operation from –40°C to 85°C.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN65LVDx10x Differential Translator/Repeater datasheet (Rev. E) | PDF | HTML | 2015/07/20 |
| Application note | Signaling Rate vs. Distance for Differential Buffers | 2010/01/26 | ||
| Application note | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007/10/17 | ||
| Application note | DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML | 2003/02/19 | ||
| EVM User's guide | 2-GBPS Differential Repeater EVM (Rev. A) | 2002/11/11 | ||
| More literature | HPL EVM Program | 2002/08/29 | ||
| EVM User's guide | 2-GBPS Differential Repeater EVM | 2002/08/08 |
설계 및 개발
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SN65CML100EVM — SN65CML100 평가 모듈
The EVM allows evaluation of operation of theSN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters. Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can beobserved across on board terminations, or via direct connection to 50-ohm (...)
SN65LVDS101EVM — SN65LVDS101 평가 모듈
The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters. Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
TIDA-01378 — 업스트림 DOCSIS 3.1 애플리케이션을 위한 광대역 리시버 레퍼런스 디자인
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.