인터페이스 HDMI, 디스플레이 포트 및 MIPI IC

TMDS261B

활성

적응형 이퀄라이제이션을 지원하는 3Gbps 2-To-1 HDMI/DVI 멀티플렉서

제품 상세 정보

Type Mux Protocols HDMI Rating Catalog Speed (max) (Gbpp) 3 Number of channels 2 Supply voltage (V) 3.3 Operating temperature range (°C) 0 to 70
Type Mux Protocols HDMI Rating Catalog Speed (max) (Gbpp) 3 Number of channels 2 Supply voltage (V) 3.3 Operating temperature range (°C) 0 to 70
TQFP (PAG) 64 144 mm² 12 x 12
  • 2:1 Sink-side switch Supporting DVI Above 1920 × 1200
    and HDMI HDTV Resolutions up to 1080p With 16-Bit Color Depth
  • Designed for Signaling Rates up to 3 Gbps
  • Supports HDMI 1.3a Specification
  • Adaptive Equalization on inputs to support up to 20-m HDMI Cable
    at 2.25 Gbps for 1080p 12-Bit Color Depth
  • TMDS Input Clock-Detect Circuit
  • DDC Repeater Function
  • <2-mW Low-Power Mode
  • Local I2C or GPIO Configurable
  • Enhanced ESD. HBM: 10 kV on All Input TMDS, DDC I2C, HPD Pins
  • 3.3-Volt Power Supply
  • Temperature Range: 0°C to 70°C
  • 64-Pin TQFP Package: Pin-Compatible With TMDS251
  • Robust TMDS Receive Stage That Can Work With Non-Compliant Input
    Common-Mode HDMI Signal
  • APPLICATIONS
    • High-Definition Digital TV
      • LCD
      • Plasma
      • DLP

DLP is a trademark of Texas Instruments.

  • 2:1 Sink-side switch Supporting DVI Above 1920 × 1200
    and HDMI HDTV Resolutions up to 1080p With 16-Bit Color Depth
  • Designed for Signaling Rates up to 3 Gbps
  • Supports HDMI 1.3a Specification
  • Adaptive Equalization on inputs to support up to 20-m HDMI Cable
    at 2.25 Gbps for 1080p 12-Bit Color Depth
  • TMDS Input Clock-Detect Circuit
  • DDC Repeater Function
  • <2-mW Low-Power Mode
  • Local I2C or GPIO Configurable
  • Enhanced ESD. HBM: 10 kV on All Input TMDS, DDC I2C, HPD Pins
  • 3.3-Volt Power Supply
  • Temperature Range: 0°C to 70°C
  • 64-Pin TQFP Package: Pin-Compatible With TMDS251
  • Robust TMDS Receive Stage That Can Work With Non-Compliant Input
    Common-Mode HDMI Signal
  • APPLICATIONS
    • High-Definition Digital TV
      • LCD
      • Plasma
      • DLP

DLP is a trademark of Texas Instruments.

The TMDS261B is a two-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to two DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth. TMDS261B device is not intended for source side applications such as external switch boxes

The TMDS261B provides an adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps (see ).

DLP is a trademark of Texas Instruments.

When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.

The TMDS261B is designed to be controlled via a local I2C interface or GPIO interface, based on the status of the I2C_SEL pin. The local I2C interface in TMDS261B is a slave-only I2C interface. (See the section.)

I2C Mode: When the I2C_SEL pin is set low, the device is in I2C mode. With local I2C, the interface port status can be read, and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature, and TMDS input-port selection can be set..

GPIO mode: When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default DDC I2C buffer OVS setting (OVS3) is set. See and the for a detailed description of the DDC I2C buffer.

Following are some of the key features (advantages) that the TMDS261B provides to the overall sink-side system (HDTV).

  • 2×1 switch that supports TMDS data rates up to 3 Gbps on both input ports.
  • ESD: Built-in support for high ESD protection (up to 10 kV on the HDMI source side). The HDMI source-side pins on the TMDS261B are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.
  • Adaptive equalization: The built-in adaptive equalization support compensates for intersymbol interference [ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Adaptive equalization adjusts the equalization gain automatically, based on the cable length and the incoming TMDS data rate.
  • TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures that the TMDS output port is turned on only if there is a valid TMDS input signal. The TMDS clock-detect feature can be by-passed in I2C mode; see and . It is recommended to enable TMDS clock-detect circuitry during normal operation. However, for HDMI compliance testing (TMDS termination-voltage test), the clock-detect feature should be disabled by using the I2C mode control. If the customer requires passing the TMDS termination-voltage test in the GPIO mode with the default TMDS clock-detect circuitry enabled, then a valid TMDS clock should be provided for this compliance test, so that the terminations on the TMDS data pair can be connected and thus customer can pass the TMDS termination-voltage test.
  • DDC I2C buffer: This feature provides isolation on the source-side and sink-side DDC I2C capacitance, thus helping the sink system to pass system-level compliance.
  • Robust TMDS receive stage: This feature ensures that the TMDS261B can work with TMDS input signals having common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI specifications.
  • VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS swing of the TMDS261B (if needed) based on the system requirements.
  • GPIO or local I2C interface to control the device features
  • TMDS output edge-rate control: This feature adjusts the TMDS261B TMDS output rise and fall times. There are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV) in passing regulatory EMI compliance.

The TMDS261B is a two-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to two DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth. TMDS261B device is not intended for source side applications such as external switch boxes

The TMDS261B provides an adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps (see ).

DLP is a trademark of Texas Instruments.

When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.

The TMDS261B is designed to be controlled via a local I2C interface or GPIO interface, based on the status of the I2C_SEL pin. The local I2C interface in TMDS261B is a slave-only I2C interface. (See the section.)

I2C Mode: When the I2C_SEL pin is set low, the device is in I2C mode. With local I2C, the interface port status can be read, and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature, and TMDS input-port selection can be set..

GPIO mode: When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default DDC I2C buffer OVS setting (OVS3) is set. See and the for a detailed description of the DDC I2C buffer.

Following are some of the key features (advantages) that the TMDS261B provides to the overall sink-side system (HDTV).

  • 2×1 switch that supports TMDS data rates up to 3 Gbps on both input ports.
  • ESD: Built-in support for high ESD protection (up to 10 kV on the HDMI source side). The HDMI source-side pins on the TMDS261B are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.
  • Adaptive equalization: The built-in adaptive equalization support compensates for intersymbol interference [ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Adaptive equalization adjusts the equalization gain automatically, based on the cable length and the incoming TMDS data rate.
  • TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures that the TMDS output port is turned on only if there is a valid TMDS input signal. The TMDS clock-detect feature can be by-passed in I2C mode; see and . It is recommended to enable TMDS clock-detect circuitry during normal operation. However, for HDMI compliance testing (TMDS termination-voltage test), the clock-detect feature should be disabled by using the I2C mode control. If the customer requires passing the TMDS termination-voltage test in the GPIO mode with the default TMDS clock-detect circuitry enabled, then a valid TMDS clock should be provided for this compliance test, so that the terminations on the TMDS data pair can be connected and thus customer can pass the TMDS termination-voltage test.
  • DDC I2C buffer: This feature provides isolation on the source-side and sink-side DDC I2C capacitance, thus helping the sink system to pass system-level compliance.
  • Robust TMDS receive stage: This feature ensures that the TMDS261B can work with TMDS input signals having common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI specifications.
  • VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS swing of the TMDS261B (if needed) based on the system requirements.
  • GPIO or local I2C interface to control the device features
  • TMDS output edge-rate control: This feature adjusts the TMDS261B TMDS output rise and fall times. There are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV) in passing regulatory EMI compliance.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
1개 모두 보기
유형 직함 날짜
* Data sheet 2 Port HDMI switch datasheet (Rev. A) 2011/07/18

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
TQFP (PAG) 64 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상