TPD5S115
- Conforms to HDMI Compliance Tests Without Any External Components
- Supports HDMI 2.0, HDMI 1.4, and HDMI 1.3 Standards
- Matches HDMI Connector Pin Mapping
- Internal DC-DC Converter to Generate 5 V From a Battery Voltage as Low as 2.3 V
- Auto-Direction Sensing, Level Shifting, and Buffering in the CEC, SDA, and SCL Paths
- IEC 61000-4-2 (Level 4) System Level ESD Compliance
- Reverse Current Blocking and Short-Circuit Protection to Protect Against Fault Conditions
- Industrial Temperature Range: –40°C to 85°C
The TPD5S115 device is an integrated HDMI companion chip solution. The device provides a regulated 5-V output (5VOUT) for sourcing the HDMI power line. The regulated 5-V output supplies up to 55 mA to the HDMI receiver with a current limiting function. The TPD5S115 features two control signals: EN and LS_OE. The control of 5VOUT and the hot plug detect (HPD) circuitry is independent of the LS_OE control signal and is controlled by the EN pin. The EN pin allows the detection scheme (5VOUT + HPD) to be active before turning on the whole HDMI link. The LS_OE activates the internal LDO, CEC, SCL, and SDA buffers only when EN is also activated. This dual stage enable scheme ensures optimized power saving for portable applications.
There are three noninverting, bidirectional, voltage level translation circuits for the SDA, SCL, and CEC lines. Each have a common power rail (VCCA) on the A side from 1.1 V to 3.6 V. On the B side, the SCL_B and SDA_B each have an internal 1.75-kΩ pullup connected to the regulated 5-V rail (5VOUT). The DDC (SCL_B and SDA_B) pins meet the I2C specification and drive up to 750-pF loads with the buffers. The CEC_B pin has an internal 27-kΩ pullup to an internal 3.3-V supply. The TPD5S115 exceeds the IEC61000-4-2 (Level 4) ESD protection level. This device features a space saving, 1.72-mm × 1.72-mm, YFF package with 0.4-mm pitch.
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | TPD5S115 HDMI Companion Chip With Step-Up DC-DC Converter, Level-Shifter, and ESD Clamp datasheet (Rev. D) | PDF | HTML | 2017/06/08 |
User guide | Reading and Understanding an ESD Protection Data Sheet (Rev. A) | PDF | HTML | 2023/09/19 | |
Selection guide | System-Level ESD Protection Guide (Rev. D) | 2022/09/07 | ||
Application note | ESD Protection Layout Guide (Rev. A) | PDF | HTML | 2022/04/07 | |
White paper | Designing USB for short-to-battery tolerance in automotive environments | 2016/02/10 | ||
Analog Design Journal | Design Considerations for System-Level ESD Circuit Protection | 2012/09/25 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
DSBGA (YFF) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.