홈 전원 관리 멀티 채널 IC(PMIC)
홈
전원 관리
멀티 채널 IC(PMIC)

TPS51116

활성

완전한 DDR, DDR2, DDR3, DDR3L, LPDDR3 및 DDR4 전원 솔루션 동기 벅 컨트롤러, 3A LDO

지금 주문
데이터 시트

TPS51116

활성
데이터 시트 지금 주문

제품 상세 정보

Vin (min) (V) 3 Vin (max) (V) 28 Vout (min) (V) 0.75 Vout (max) (V) 3 Features Complete Solution, Shutdown Pin for S3 Iq (typ) (mA) 0.8 Rating Catalog Operating temperature range (°C) -40 to 85 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 3 Vin (max) (V) 28 Vout (min) (V) 0.75 Vout (max) (V) 3 Features Complete Solution, Shutdown Pin for S3 Iq (typ) (mA) 0.8 Rating Catalog Operating temperature range (°C) -40 to 85 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4 VQFN (RGE) 24 16 mm² 4 x 4
  • Synchronous Buck Controller (VDDQ)
    • Wide-Input Voltage Range: 3.0-V to 28-V
    • D−CAP™ Mode with 100-ns Load Step Response
    • Current Mode Option Supports Ceramic Output Capacitors
    • Supports Soft-Off in S4/S5 States
    • Current Sensing from RDS(on) or Resistor
    • 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
      1.5-V (DDR3), 1.35-V (DDR3L), 1.2-V (LPDDR3 and DDR4) or
      Output Range 0.75-V to 3.0-V
    • Equipped with Powergood, Overvoltage Protection and Undervoltage Protection
  • 3-A LDO (VTT), Buffered Reference (VREF)
    • Capable to Sink and Source 3 A
    • LDO Input Available to Optimize Power Losses
    • Requires only 20-µF Ceramic Output Capacitor
    • Buffered Low Noise 10-mA VREF Output
    • Accuracy ±20 mV for both VREF and VTT
    • Supports High-Z in S3 and Soft-Off in S4/S5
    • Thermal Shutdown
  • Synchronous Buck Controller (VDDQ)
    • Wide-Input Voltage Range: 3.0-V to 28-V
    • D−CAP™ Mode with 100-ns Load Step Response
    • Current Mode Option Supports Ceramic Output Capacitors
    • Supports Soft-Off in S4/S5 States
    • Current Sensing from RDS(on) or Resistor
    • 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
      1.5-V (DDR3), 1.35-V (DDR3L), 1.2-V (LPDDR3 and DDR4) or
      Output Range 0.75-V to 3.0-V
    • Equipped with Powergood, Overvoltage Protection and Undervoltage Protection
  • 3-A LDO (VTT), Buffered Reference (VREF)
    • Capable to Sink and Source 3 A
    • LDO Input Available to Optimize Power Losses
    • Requires only 20-µF Ceramic Output Capacitor
    • Buffered Low Noise 10-mA VREF Output
    • Accuracy ±20 mV for both VREF and VTT
    • Supports High-Z in S3 and Soft-Off in S4/S5
    • Thermal Shutdown

The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, DDR3L, LPDDR3 and DDR4 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The device offers the lowest total solution cost in systems where space is at a premium. The synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The device supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The device has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4 × 4 QFN.

The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, DDR3L, LPDDR3 and DDR4 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The device offers the lowest total solution cost in systems where space is at a premium. The synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The device supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The device has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4 × 4 QFN.
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기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
18개 모두 보기
유형 직함 날짜
* Data sheet TPS51116 Complete DDR, DDR2, DDR3, DDR3L, LPDDR3 and DDR4 Power Solution Synchronous Buck Controller, 3-A LDO, Buffered Reference datasheet (Rev. J) PDF | HTML 2017/11/16
Analog Design Journal Control-Mode Quick Reference Guide (Rev. B) PDF | HTML 2023/08/29
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020/07/09
Selection guide Power Management Guide 2018 (Rev. R) 2018/06/25
Technical article Design advantage of D-CAP control topology PDF | HTML 2017/04/13
Technical article D-CAP3 – A sequel better than the original PDF | HTML 2015/05/07
More literature Computing DDR DC-DC Power Solutions 2012/08/22
Application note Intel Core i3, i5, i7 [Arrandale] Reference Design 2010/07/21
Application note Intel EP80579 Tolopai System-on-Chip Reference Design 2010/07/21
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 2010/04/28
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 2010/04/20
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 2010/03/31
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 2010/03/26
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 2010/03/26
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 2010/03/26
User guide Using the TPS51116 (Rev. A) 2008/11/12
Application note Cyclone™ III FPGA Starter Kit Power Reference Design 2008/03/27
Application note DDR2 Power Solutions for Notebooks 2004/05/24

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

TPS51116EVM-001 — TPS51116 메모리 전원 솔루션, 동기 벅 컨트롤러 평가 모듈

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

TPS51116 PSpice Transient Model (Rev. B)

SLIM076B.ZIP (101 KB) - PSpice Model
다운로드
시뮬레이션 모델

TPS51116 TINA-TI Transient Reference Design

SLUM166.TSC (224 KB) - TINA-TI Reference Design
다운로드
시뮬레이션 모델

TPS51116 TINA-TI Transient Spice Model

SLUM167.ZIP (58 KB) - TINA-TI Spice Model
다운로드
레퍼런스 디자인

PMP1516 — DDR 또는 DDR2 메모리 애플리케이션을 위한 완벽한 전원 솔루션

This DDR reference design provides a VDDQ of 2.5V @ 6A and a VTT of 1.25V. The 2.5V sync buck converter achieves an efficiency of 92% while the 1.25V minimizes area by implementing a built-in LDO and has excellent tracking performance.
Test report: PDF
회로도: PDF
레퍼런스 디자인

PMP2543 — Altera Cyclone III FPGA 전원 관리 레퍼런스 디자인

The Cyclone III power management design is a complete, non-isolated power solution and provides all 5 required rails for powering the FPGA. The design also includes complete power solutions for DDR Memory VTT and VDDQ rails and USB power. This design is optimized to power the Altera 3C25F324 (...)
Test report: PDF
회로도: PDF
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
HTSSOP (PWP) 20 Ultra Librarian
VQFN (RGE) 24 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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