TPS51200

Name: TPS51200
Brand: TI
SKU: TPS51200
Price: 0.255 USD

활성

VTTREF 버퍼 레퍼런스가 내장된 DDR2, DDR3, DDR3L, DDR4용 3A 싱크/소스 DDR 터미네이션 레귤레이터

지금 주문

데이터 시트

document-pdfAcrobat TPS51200 Sink and Source DDR Termination Regulator datasheet (Rev. D) (영어) PDF | HTML

TPS51200

활성

데이터 시트

지금 주문

제품 상세 정보

Vin (min) (V)

1.1

Vin (max) (V)

3.5

Vout (max) (V)

1.8

Features

S3/S5 Support

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Iq (typ) (mA)

0.5

Product type

DDR

DDR memory type

DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3

Vin (min) (V)

1.1

Vin (max) (V)

3.5

Vout (max) (V)

1.8

Features

S3/S5 Support

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Iq (typ) (mA)

0.5

Product type

DDR

DDR memory type

DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3

VSON (DRC)

9 mm² 3 x 3

Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
VLDOIN Voltage Range: 1.1 V to 3.5 V
Sink and Source Termination Regulator Includes Droop Compensation
Requires Minimum Output Capacitance of 20-µF (Typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
PGOOD to Monitor Output Regulation
EN Input
REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
Remote Sensing (VOSNS)
±10-mA Buffered Reference (REFOUT)
Built-in Soft Start, UVLO, and OCL
Thermal Shutdown
Supports DDR, DDR2, DDR3, DDR3L, Low-Power DDR3, and DDR4 VTT Applications
10-Pin VSON Package With Thermal Pad

Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
VLDOIN Voltage Range: 1.1 V to 3.5 V
Sink and Source Termination Regulator Includes Droop Compensation
Requires Minimum Output Capacitance of 20-µF (Typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
PGOOD to Monitor Output Regulation
EN Input
REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
Remote Sensing (VOSNS)
±10-mA Buffered Reference (REFOUT)
Built-in Soft Start, UVLO, and OCL
Thermal Shutdown
Supports DDR, DDR2, DDR3, DDR3L, Low-Power DDR3, and DDR4 VTT Applications
10-Pin VSON Package With Thermal Pad

The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20 µF. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200 is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200 is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

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23개 모두 보기

	유형	직함		날짜
*	Data sheet	TPS51200 Sink and Source DDR Termination Regulator datasheet (Rev. D)	PDF \| HTML	2020/03/19
	Application note	LDO Noise Demystified (Rev. B)	PDF \| HTML	2020/08/18
	Application note	DDR VTT Power Solutions: A Competitive Analysis (Rev. A)		2020/07/09
	Application note	Point-of-Load Solutions for Data Center App Implementing VR13.HC Vccin Spec (Rev. A)	PDF \| HTML	2020/01/08
	Selection guide	Power Management Guide 2018 (Rev. R)		2018/06/25
	Application note	LDO PSRR Measurement Simplified (Rev. A)	PDF \| HTML	2017/08/09
	Test report	TI Power Reference Design for Xilinx(R) Virtex(R)-7 (VC709) (Rev. A)		2014/12/16
	Test report	TI Power Reference Design for Xilinx® Kintex®-7 (KC705) (Rev. A)		2014/12/16
	User guide	TI Power Reference Design for Xilinx® Zynq 7000 (ZC702) (Rev. A)		2014/12/16
	Test report	PMP7977 Test Results (Rev. A)		2014/06/11
	Test report	TI Power Reference Design for Xilinx® Artix®-7 (AC701)		2014/05/12
	User guide	PMP7977 User's Guide		2013/09/11
	More literature	Computing DDR DC-DC Power Solutions		2012/08/22
	Application note	Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A)		2010/05/24
	Application note	Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs		2010/04/28
	Application note	Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices		2010/04/20
	Application note	Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472)		2010/03/31
	Application note	'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472)		2010/03/26
	Application note	Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs		2010/03/26
	Application note	TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers		2010/03/26
	White paper	Spartan 6 LX150T Modular Solution		2009/10/14
	User guide	Virtex 6 LX130T Module design		2009/08/27
	EVM User's guide	Using the TPS51200 Evaluation Module		2008/05/28

설계 및 개발

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평가 보드

TPS51200EVM — TPS51200 싱크 소스 DDR 터미네이션 레귤레이터

TPS51200EVM 평가 보드인 HPA322A는 TI의 비용에 최적화된 DDR/DDR2/DDR3/LP DDR3 VTT 터미네이션 레귤레이터인 TPS51200의 성능과 특성을 평가하도록 설계되었습니다. TPS51200은 최소한의 외부 부품으로 DDR(2.5V/1.25V), DDR2(1.8V/0.9V), DDR3(1.5V/0.75V), LP DDR3(1.2V/0.6V) 사양을 지원하는 DDR 메모리에 적절한 터미네이션 전압 및 10mA 버퍼 레퍼런스 전압을 제공하도록 설계되었습니다.

사용 설명서: PDF